CLIP Tutorial, Part 3: Adding CLIP to a Project (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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	LabVIEW 2016 FPGA Module Help
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	LabVIEW 2020 FPGA Module Help

You add a component-level IP (CLIP) item to the LabVIEW project to instantiate the CLIP inside the FPGA.

Complete the following steps to add a CLIP item in a project:

1. Create a new project and save the project as CLIP Demo.lvproj.
2. Add an FPGA target that supports CLIP to the project.
3. Right-click the FPGA target and select Properties from the shortcut menu to display the FPGA Target Properties dialog box.
4. Select Component-Level IP from the Category list to display the Component-Level IP Properties page.
5. Click the Add button, select the DemoClipAdder.xml file, and click the OK button.

   Note  The CLIP wizard automatically adds the declaration XML file to the project.

6. Click the OK button to close the FPGA Target Properties dialog box.
7. Right-click the FPGA target in the Project Explorer window and select New»Component-Level IP from the shortcut menu.
8. On the General page of the Component-Level IP Properties dialog box, enter Adder CLIP in the Name field and select DemoClipAdder from the Component-Level IP Declaration pull-down menu.
9. (Optional) On the Clock Selections page, select a clock. By default, the DemoClipAdder example uses the top-level FPGA clock, so you do not need to change the clock.
10. Click the OK button. Notice that the Project Explorer window now includes a CLIP item, as well as the I/O defined in the declaration XML file.