CLIP Tutorial, Part 2: Defining the Interface (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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To add IP as a component-level IP (CLIP) item in a LabVIEW project, the IP must have an accompanying declaration XML file to define the I/O for LabVIEW.

You can use the Configure Component-Level IP wizard to create this file automatically from the example DemoClipAdder.vhd file. Complete the following steps to create the declaration XML file using the CLIP wizard.

  1. Right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu.
  2. On the Component-Level IP page of the FPGA Target Properties dialog box, click the Create File button.
  3. On the Name and Source page of the CLIP wizard, click the Add Synthesis File button.
  4. Select DemoClipAdder.vhd and click the OK button to add the file.
  5. (Optional) Select (Xilinx ISE) DemoClipAdder.ucf or (Xilinx Vivado) DemoClipAdder.xdc and click the OK button to add the file.
  6. Click the Next button.
  7. Follow the instructions in the rest of the CLIP wizard to finish creating the declaration XML file.
    Tip  Click the Help button on each page of the wizard for more information about the available options.
  8. Click the Finish button to complete the configuration and create the declaration XML file.

The CLIP wizard automatically adds the CLIP to the project.


Previous: CLIP Tutorial, Part 1: Creating VHDL Code Next: CLIP Tutorial, Part 3: Adding CLIP to a Project

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