Using the Configure Component-Level IP Wizard (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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Use the Configure Component-Level IP wizard (CLIP wizard) to define the IP interface without editing the declaration XML file by hand. You can use this wizard to create or modify a declaration XML file. The CLIP wizard also can check the syntax of the VHDL you are using in the CLIP. Depending on the action you want to perform, launch the CLIP wizard from the Component-Level IP page of the FPGA Target Properties dialog box in either of the following ways:

  • To generate a new CLIP interface, click the Create File button.
  • To modify an existing CLIP interface, select the declaration file and click the Modify File button.
Note  You must have the necessary Xilinx compilation tools installed on the local computer to use this wizard. Refer to the support document at for more information about NI hardware supported by each Xilinx compilation tool. Refer to the Xilinx Compilation Tools Readme for instructions on installing Xilinx compilation tools for LabVIEW.

The CLIP wizard contains the following pages:

  1. Name and Source
  2. Entity, Architecture, FPGA Family and IP Type
  3. Generics
  4. Basic Signal Settings
  5. Additional Clock Signal Settings
  6. Additional Clock Status Signal Settings
  7. Additional Data Signal Settings
  8. XML Export

Configuring a CLIP to Use with Simulation

With the wizard you can specify simulation models for CLIP so that you can export FPGA VIs containing CLIP for third-party simulation. If you are going to create simulation exports of FPGA VIs containing CLIP, you must define the simulation behavior for the CLIP synthesis files in the Name and Source page of the wizard.


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