Debugging FPGA VIs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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LabVIEW provides several ways to test and debug all or parts of an FPGA VI. Refer to the following table when deciding what execution mode you should use for verification and debugging.

Execution Mode Verify Functional Performance Verify Timing Verify Integration of HDL IP Good for Unit Testing Good for Component Testing Good for System Testing
Windows PC

Simulation Mode

FPGA Target

Third-Party Simulation

Note  You also can use interactive front panel communication to debug your FPGA VIs on certain targets.

If you are able to debug and verify extensively at the unit and component levels, you will have less verification to do at the system level. Refer to the following sections for guidelines on identifying a unit, component, and system.

Unit

The unit is the most fundamental level of IP you can build. It maps to a specific processing function or algorithm and it does not make much sense to split and test it as a set of smaller functional units. Code that is considered a unit may have one or more of the following characteristics:

  • It does not include any I/O, data communication, or target resources
  • It does not have multiple loops running in parallel or at different rates
  • You can provide some known inputs and test for expected outputs
  • It does not rely on the explicit specific passing or control of time
  • It can be called as a subVI that you may want to reuse in other part of your design

Component

Components are more complex pieces of logic that rely on the timing in the system. Components are modular and usually have a clear task or objective to accomplish. You can usually break an FPGA VI down into multiple components. The verification at this level makes sure that the components interact as expected when integrated into a system. You also may want to make sure that a subcomponent is interacting properly with the I/O or host VI without having to wait until the whole system is assembled.

System

The system level is the top-most component, represented by your top-level FPGA VI plus any additional HDL IP imported through CLIP. A system usually contains multiple While Loops or single-cycle Timed Loops. The system interface is exposed to the host application, so verification tests are either very similar in nature to running your host application or include your host application. Verification at the system level requires you to use the host interface API and to connect all real I/O signals to your system.

Related Information

Interactive Front Panel Communication

Debugging FPGA VIs Using Simulation Mode

Debugging FPGA VIs on an FPGA Target

Debugging FPGA VIs Using a Third-Party Simulator

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