Implementing Block Memory FIFOs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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When you implement block memory FIFOs, the actual number of elements the FIFO can hold depends on the factors outlined in this topic.

Implementing FIFOs with Slice Fabric Control Logic

If you implement a FIFO using block memory with the Slice Fabric control logic, the considerations in the following table apply to the actual number of elements the FIFO can hold:

FIFO Type Size to Specify Considerations
Target-scoped FIFOs A power of two plus a small number of elements The General page displays a size of 2^M+5, where M is the address width. LabVIEW coerces Requested Number of Elements to the closest larger value that is 2^M+5. For example, if Requested Number of Elements is 1,000, LabVIEW coerces this number to 1,029. If the FPGA does not have enough space for the coerced Requested Number of Elements, the FPGA VI fails to compile.
DMA FIFOs
  • One less than a power of two for Target to Host - DMA
  • One less than a power of two plus six times the Number of Elements to Read for Host to Target - DMA
The General page displays a size of 2^M-1 or 2^M+(6*NumberofElementstoRead)-1, where M is the address width. LabVIEW coerces Requested Number of Elements to the closest larger valid value. If the FPGA does not have enough space for the coerced Requested Number of Elements, the FPGA VI fails to compile. You must implement DMA FIFOs using block memory with Slice Fabric control logic. Maximum DMA FIFO size varies by target. Refer to the specific FPGA target hardware documentation for more information about DMA FIFO size limitations.
Peer-to-peer FIFOs
  • One less than a power of two for writer FIFOs
  • One less than a power of two plus six times the Number of Elements to Read for reader FIFOs
The General page displays a size of 2^M-1 or 2^M+(6*NumberofElementstoRead)-1, where M is the address width. LabVIEW coerces Requested Number of Elements to the closest larger valid value. If the FPGA does not have enough space for the coerced Requested Number of Elements, the FPGA VI fails to compile. You must implement peer-to-peer FIFOs using block memory with Slice Fabric control logic.

Implementing FIFOs with Built-In Control Logic

If you implement a FIFO using block memory with the Built-In control logic, the following considerations apply to the actual number of elements the FIFO can hold:

  • Enabling the handshaking interface on the Write method increases FIFO depth by one.
  • Target-scoped FIFOs—LabVIEW coerces Requested Number of Elements to a depth that you can implement using the built-in FIFOs. The calculation for the coerced Requested Number of Elements varies depending on FPGA families. If the FPGA does not have enough space for the coerced Requested Number of Elements, the FPGA VI fails to compile.
Note   Built-in FIFOs and target-optimal FIFOs are not supported in simulation exports. You can use Conditional Disable structures to implement slice-fabric FIFOs for simulation exports.

Implementing FIFOs with Target Optimal Control Logic

If you implement a FIFO using block memory with the Target Optimal control logic, all the considerations in this topic apply to the actual number of elements the FIFO can hold because target-optimal control logic is a combination of built-in and slice fabric control logic.

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