Filtering FPGA I/O Using Multiple Input Channels (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Use the filtering VIs on the FPGA Math & Analysis palette to filter FPGA I/O. By default, the FPGA filtering VIs accept a single input channel. However, you can use the Number of channels option in the configuration dialog box of the filtering VI to configure the VI for multiple input channels. The following filtering VIs support multiple input channels:

When you configure an FPGA filtering VI for multiple input channels, you must send each input channel to the filter VI in succession. You can bundle the input channels into an array and use a For Loop to ensure that the filter VI receives each input channel in succession, as shown in the following block diagram.

In the previous block diagram, four analog input signals pass through a Butterworth Filter and a Notch Filter. To maximize throughput, the VI uses Feedback Nodes to create a pipeline.

Note  Some FPGA targets support the IO Sample method, which provides data from multiple input channels in succession. If the target supports the IO Sample Method, you do not need to bundle input channels into an array. Instead, include the FPGA I/O Method Node configured with the IO Sample method inside the For Loop.

Some filtering VIs that support multiple channels also support handshaking with multiple channels.

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