Troubleshooting Timing Violations (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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You can use the following strategies to troubleshoot a timing violation that appears in the Timing Violation Analysis window.

• If the target supports the Xilinx Options page, change some of the compilation options.
• Reduce long combinatorial paths.
• Use pipelining.
• Reduce the number of nested Case Structures.
• Use smaller data types.
• Recompile the FPGA VI. Because the compilation process non-deterministically maps the FPGA VI to the FPGA, the process does not produce the same results each time you compile an FPGA VI. Therefore, if the FPGA VI missed the required clock rate by only a few nanoseconds, recompiling the FPGA VI might fix the timing violation.
• Reduce the clock rate of the application.
• Remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes on the block diagram. This strategy is most useful for very large designs.