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Jitter occurs if a requestor in a loop is delayed in becoming an accessor due to resource contention with one or more additional requestors, and the delay varies per loop iteration. For example, you might have an application performing a timed While Loop that samples analog input at a fixed rate. Each time the FPGA I/O Node executes, the node becomes an accessor as soon as it requests the analog input resource. If you add a second timed While Loop that samples the same analog input resource, the two FPGA I/O Nodes might simultaneously request the analog input resource. In this case, the arbiter delays one of the requestors while allowing the other requestor to become an accessor. This delay introduces jitter because resource access does not always occur immediately after the request was made.
To avoid jitter, design the FPGA VI block diagram to make sure a requestor does not access the shared resource when the shared resource is busy and to make sure two requests do not occur during the same clock cycle. Jitter occurs most often when you use a shared subVI in two independent parts of the VI, or when you access a resource interface from parallel loops, as shown in the following block diagram.
The VI in the block diagram above contains parallel While Loops, both of which write to MemoryBlock1. Depending on how long it takes the rest of the code in each loop to execute, the two Memory Method Nodes might make simultaneous write requests to MemoryBlock1, resulting in both jitter and data uncertainty. In the example above, jitter occurs when Count1 and Count2 differ by 10 - 15 ticks.
The possibility of jitter grows with the number of accessors to a single resource. However, if you avoid simultaneous requests, the delay through the arbiter is constant regardless of the number of potential accessors. To avoid multiple accessors in the above example, you could create a second memory item and write to it in the bottom While Loop, as shown in the following block diagram.