LabVIEW 2018 FPGA Module Help
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Use name controls to create subVIs that can be reused with different I/O, clock, register, memory, FIFO, or handshake resources. You can use name controls only in reentrant FPGA subVIs.
||Note FPGA name controls are located on the Name Controls palette. The FPGA Module also includes block diagram constants for each of the FPGA name controls.
Complete the following steps to enable a subVI to accept an FPGA I/O, clock, register, memory, or FIFO resource.
- Place an FPGA I/O Node, Register Method Node, Memory Method Node, FIFO Method Node, or Handshake Method Node on the block diagram of your subVI. To select an FPGA clock, place a single-cycle Timed Loop on the block diagram of your subVI.
- Right-click the FPGA I/O In, Register In, Memory In, FIFO In, Handshake In, or Source Name input terminal and select Create»Control.
- Assign the I/O, register, memory, FIFO, handshake, or clock control to a connector pane terminal of the subVI.
Passing I/O, Clocks, Register Items, Memory Items, FIFOs, or Handshake Items to a SubVI
The following block diagram shows MemoryControl.vi with the memory control, Memory In, wired to a Memory Method Node.
The following block diagram shows MemoryControl.vi as the referenced subVI. Notice that the VI-Defined Memory Configuration node specifies the memory item to use in the calling VI below. This design means that if you want to execute MemoryControl.vi with a different memory item, you only have to change the item to which Memory In refers using the VI-Defined Memory Configuration node.
Restrictions on FPGA Name Controls
The following restrictions apply to FPGA I/O, cRIO I/O, memory, FIFO, handshake, and clock controls:
- You can change the value of FPGA name controls only when programming the FPGA VI. You cannot change the values while an FPGA VI runs on a development computer or when using interactive front panel communication.
- FPGA name controls are available only when programming VIs under an FPGA target. FPGA name controls are not available when programming host VIs.
- You can bundle FPGA name controls into clusters with other FPGA name controls, with occurrence refnums, and with other data types. However, you cannot have such a cluster on the front panel of the top-level FPGA VI. LabVIEW returns an error when you attempt to compile the FPGA VI.
Building the Connector Pane
Communicating with FPGA Targets from a Host Computer
Creating Modular Code
Storing Data on an FPGA Target
Transferring Data between Devices or Structures Using FIFOs
Using FPGA I/O
Using the FPGA I/O Node