|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Because they add an extra signal to the FPGA logic, implicit enable signals can create routing congestion and limit timing performance. For some applications, it may be appropriate to reduce routing congestion by allowing LabVIEW to remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes in the design.
Use the following flow chart to help determine whether your application is a candidate for removing implicit enable signals.
LabVIEW does not support the following methods and functionalities in projects in which implicit enable signals have been removed:
Complete the following steps to allow the compiler to remove the implicit enable signal from single-cycle Timed Loops that do not have data dependencies and are free-running.
|Note If the Require removal of implicit enable signals checkbox does not appear, the VI is open under a target that does not support implicit enable removal.|
Complete the following steps to require the compiler to attempt to remove the implicit enable signal from single-cycle Timed Loops. Completing this procedure causes LabVIEW to return an error when the compiler cannot remove the implicit enable signal from a single-cycle Timed Loop.
You must turn on the ability to remove implicit enable signals for each CLIP clock in your design by adding the necessary tags to ensure that the clock supports gating to the declaration XML file.