Improving Timing Performance in Large Designs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Because they add an extra signal to the FPGA logic, implicit enable signals can create routing congestion and limit timing performance. For some applications, it may be appropriate to reduce routing congestion by allowing LabVIEW to remove the implicit enable signal from single-cycle Timed Loops that run independently of other nodes in the design.

Deciding Whether to Remove Implicit Enable Signals

Applications that Might Benefit from Removing Implicit Enable Signals

  • High-throughput applications
  • Applications with single-cycle Timed Loops that run under a fast clock and contain large amounts of code
  • Applications that fail to compile after you add additional code, when you know that the additional code by itself would meet the necessary clock rate

Use the following flow chart to help determine whether your application is a candidate for removing implicit enable signals.

Restricted Functionality

LabVIEW does not support the following methods and functionalities in projects in which implicit enable signals have been removed:

  • Reset (Invoke Method)
  • Close and reset
  • Abort (Invoke Method)
  • Re-running the VI without first re-downloading
  • IP that undergoes an implicit synchronous reset before the VI begins execution
  • IP that needs a running clock when reset is asserted
  • Accessing controls, indicators, or DMA before the VI is running
  • Only remove implicit enable signals when the block diagram does not contain logic that must execute before or after the affected loop

Removing the Implicit Enable Signal from Single-Cycle Timed Loops

Removing Implicit Enable Signals from Qualified Loops

Complete the following steps to allow the compiler to remove the implicit enable signal from single-cycle Timed Loops that do not have data dependencies and are free-running.

  1. On the Information page of the Compilation Properties dialog box, place a checkmark in the Allow removal of implicit enable signals inside single-cycle Timed Loops checkbox.
    Note  If the Require removal of implicit enable signals checkbox does not appear, the VI is open under a target that does not support implicit enable removal.

Removing Implicit Enable Signals from All Loops

Complete the following steps to require the compiler to attempt to remove the implicit enable signal from single-cycle Timed Loops. Completing this procedure causes LabVIEW to return an error when the compiler cannot remove the implicit enable signal from a single-cycle Timed Loop.

  1. Double-click the input node of a single-cycle Timed Loop to display the Configure Timed Loop dialog box.
  2. Place a checkmark in the Require removal of implicit enable signals checkbox.

Enabling Implicit Enable Signal Removal for Individual CLIP Clocks

You must turn on the ability to remove implicit enable signals for each CLIP clock in your design by adding the necessary tags to ensure that the clock supports gating to the declaration XML file.

Related Information

Defining the IP Interface

Data Flow and the Enable Chain in FPGA VIs

Fixing Timing Violations

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