Dataflow and the Enable Chain in FPGA VIs (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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The enable chain is additional logic that LabVIEW adds to FPGA code to enforce dataflow on the FPGA. The enable chain consists of two parts:

  • A series of registers that run in parallel with the actual flow of data on the block diagram. This part of the enable chain only exists outside single-cycle Timed Loops.
  • An implicit enable signal that enforces dataflow inside the single-cycle Timed Loop. This signal fans out to all nodes within the loop that contain state-holding elements.

Dataflow Outside a Single-Cycle Timed Loop

LabVIEW executes code in a dataflow manner. Nodes execute when data is present on all inputs that the node needs in order to run. When the node finishes execution, the outputs of the node pass data to the next node. The following illustration shows an example of the FPGA hardware required to implement a Boolean function outside a single-cycle Timed Loop.

The enable chain guarantees that the FPGA logic executes in the same order as it appears on the LabVIEW block diagram. The illustration shows how the Boolean function is converted into FPGA logic when the function is outside a single-cycle Timed Loop. The function section of the illustration shows the Boolean logic corresponding to a Negate function on the block diagram. The enable chain section includes additional synchronization registers that only output on the rising edge of the clock.

The following illustration shows an example of FPGA hardware implementing an arithmetic operation.

Due to enable chain overhead, each function or VI takes a minimum of one clock cycle. Some functions, such as analog input operations, can take hundreds of clock cycles, depending upon the complexity of the operation and hardware limitations.

Dataflow Inside a Single-Cycle Timed Loop

Nodes that you place in a single-cycle Timed Loop do not include the register part of the enable chain. Eliminating the register overhead reduces the total space used on the FPGA because the flip-flops used for the enable chain are no longer required. Also, because the enable chain registers are not present, all operations in a single-cycle Timed Loop can complete in a single clock cycle. However, some nodes, such as the Memory Method Node or the FFT Express VI, take more than one clock cycle to execute, so the output of the node is not valid until the next iteration of the single-cycle Timed Loop. The number of clock-cycles required to obtain valid data is the latency of the node.

Understanding How the Implicit Enable Signal Affects Timing Performance

The implicit enable signal from the single-cycle Timed Loop fans out to all flops within the diagram. LabVIEW gates the clock associated with the single-cycle Timed Loop until the implicit enable signal is removed. The additional routing overhead of this fan-out can limit timing performance in large designs. If your design contains single-cycle Timed Loops that run independently of other nodes on the block diagram, consider removing the implicit enable signal from these loops to improve timing performance.

Note  Support for the removal of implicit enable signals varies by target. Refer to your target hardware documentation for more information about support for the removal of implicit enable signals.

The following represents a block diagram with code in a single-cycle Timed Loop.

The following illustration shows the VHDL representation of the above block diagram code.

Notice that by default, the implicit enable signal fans out to each node in the single-cycle Timed Loop that contains state-holding elements, such as flip-flops or block memory. This routing overhead limits timing performance for some applications.

The following illustration shows the same VHDL representation, this time with the implicit enable signal removed.


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