Synchronizing I/O in Single-Cycle Timed Loops (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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LabVIEW places synchronization registers between the FPGA hardware I/O and the FPGA I/O Node as implemented on the target FPGA. You can specify the number of synchronization registers for input data as 0, 1, or 2, and you can specify the number of synchronization registers for output data as 0 or 1. When the input is set to Auto (default), the number of synchronization registers is 2 for input data and 1 for output data.

Note  If you specify 0 synchronization registers for digital input and digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal and lead to unexpected behavior. Refer to the Example Code Setting the Number of Synchronization Registers to Zero section for example code outlining this scenario.
Caution  If you specify 0 synchronization registers for digital output resources in a Case structure nested in a single-cycle Timed Loop, LabVIEW is unable to hold the previous state of the digital output resource when the enable chain deasserts, which may result in unexpected output. NI recommends that you avoid specifying 0 synchronization registers unless you add the necessary logic to hold the previous state.

Example Code Using the Default Number of Synchronization Registers

Consider an FPGA VI with digital I/O operation running in a single-cycle Timed Loop as shown in the illustration below.

The digital input signal Digital Input 1 connects to a digital output signal Digital Output 1. The Trigger control wired to the selector terminal specifies when the application reads from the Digital Input 1 and writes to Digital Output 1 using a Case structure.

When the number of input synchronization registers is set to default of Auto, the circuit on the FPGA created as shown in the illustration below.

In this example, Digital Input 1 is a physical DIO pin on the FPGA that is connected to two synchronization registers. The first synchronization register handles the meta-stable state. The output of the second synchronization register is wired directly to a corresponding synchronization register for the Digital Output 1, which is connected to the output DIO pin on the FPGA. The Trigger control register output is connected to the enable chain input on the output synchronization register to determine when to output the signal.

Example Code: Setting the Number of Synchronization Registers to Zero

Consider the same block diagram as illustrated above, but now assume the number of synchronization registers is set to 0 for both the digital input and output. The equivalent circuit on the FPGA is shown below.

Here, the digital input signal Digital Input 1 has a direct hardwire connection to the digital output signal Digital Output 1 on the FPGA. The compilation process does not include any control logic to determine when to read Digital Input 1 and write Digital Output 1. In this case, the digital I/O lines are connected to each other as soon as the bitfile is downloaded to the FPGA.

Example Code: Using Zero Synchronization Registers and a Logic Function

If you must set the number of I/O synchronization registers to 0 inside a single-cycle Timed Loop and you are not satisfied with the behavior described in Example Code: Setting the Number of Synchronization Registers to Zero, you must make sure that the application contains logic between the input and the output. By adding logic between the I/O input and output, you avoid creating a direct wire connection that runs independently of the controlling logic. The following block diagram illustrates one option for implementing code with no synchronization registers.

The block diagram above uses an And function instead of a Case structure to control whether the signal reaches Digital Output 1. The Digital Input 1 node and the Trigger control are the input to the And function and the output of the And function connects to the Digital Output 1 node. The equivalent circuit on the FPGA is shown below.

The circuit above is similar to the circuit in the Example Code: Using the Default Number of Synchronization Registers in that the connection between Digital Input 1 and Digital Output 1 is made only when the Trigger control is set to TRUE. However, the circuit is different in that there are no synchronization registers on the signal path between Digital Input 1 and Digital Output 1. Digital Output 1 may be changing independently of the clock controlling the single-cycle Timed Loop.

Note  The combinatorial logic used to implement the logic of the And function can cause glitches on the output signal and lead to undesirable behavior.

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