Integrating Changes to the VHDL Test Bench (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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During third-party simulation, you might edit the FPGA VI and build the simulation export again. In some cases, you also must integrate corresponding changes into the VHDL test bench.

When to Integrate Changes Into the Test Bench File

You must integrate changes into the test bench file in the user directory in the following cases:

  • You edit properties of the FPGA target in the Project Explorer window.
  • You change items in the Project Explorer window, such as adding, removing, or renaming FIFOs.
  • You add or remove controls and/or indicators in the FPGA VI.

The File and Directory Structure for Simulation Exports

A simulation export is a collection of files necessary for simulation. You must access the simulation export directory to edit the test bench file. LabVIEW organizes the simulation export files in the following directory structure:

  • Top-level destination directory—The directory you specify on the Information page of the Simulation Export Properties dialog box.
    • user—Contains the test bench file that you must edit. LabVIEW does not overwrite files in this directory.
      Note  If the installed third-party simulator is a Xilinx simulator, you must run RegenerateIsim.bat, located in the user directory, to regenerate the simulation executable after you make changes to the generated test bench.
    • niFpga—Contains the latest test bench template and other simulation files. Do not edit the files in this directory. Every time you build a simulation export, LabVIEW overwrites the files in this directory.
    • isim(Xilinx Simulator) Contains the project file for a Xilinx Simulator. You can right-click the simulation export build specification in LabVIEW and select Launch Simulator from the shortcut menu to open the project file in a Xilinx Simulator.


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