|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
As FPGA designs get larger and more complicated, debugging designs on the FPGA chip becomes less efficient because of the time necessary for compiling and downloading to the target. Along with other debugging techniques, third-party simulation can help you test the timing behavior of FPGA VI components. Cycle-accurate third-party simulation means that timing is precise but the simulation might not use the exact hardware model to implement it.
|Note Not all targets support third-party simulation. When the FPGA target supports simulation, you have the option to create a simulation export from the Build Specifications shortcut menu.|
To use third-party simulation, you must be familiar with the Xilinx simulator and install the Xilinx compilation tools necessary for your hardware configuration.
Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool. Refer to the Xilinx Compilation Tools Readme for instructions on installing Xilinx compilation tools for LabVIEW.
You can use the Xilinx simulator to modify the VHDL test bench template that LabVIEW creates if you are familiar with VHDL. You must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards.
In the following illustration, the combined shaded areas indicate the parts that make up the test bench. LabVIEW generates the test bench template in VHDL. You then can edit the LabVIEW host VI to customize interactions with controls, indicators, and other LabVIEW objects. In addition, you can create stimulus and response models for the I/O within the VHDL test bench.