Storing Data between Loop Iterations (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Feedback Nodes

Feedback Nodes use FPGA resources to store data. Use a Feedback Node to store data, such as state information, from one VI execution or loop iteration to the next. When a Feedback Node receives a new value, the node stores the value until the node passes that value to the next input terminal. To store samples of data for multiple subsequent iterations, increase the value of Delay on the Configuration page of the Properties dialog box to delay the output of the Feedback Node.

Note  The Discrete Delay function behaves similarly to a Feedback Node. In some cases, it may be appropriate to use a Discrete Delay function rather than a Feedback Node. Refer to the table in the Discrete Delay function help topic to determine which function suits your needs.

The following example VI uses a Feedback Node. This VI runs a For Loop for n iterations. The VI then multiplies a constant value of 3 by the value stored in the Feedback Node and returns the product. The Feedback Node has a value of 1 on the first call of the VI. Given n iterations, Product is 3n.

Complete the following steps to create a Feedback Node.

  1. Display the block diagram of the FPGA VI.
  2. From the Functions palette, select Programming»Structures»Feedback Node and add it to the block diagram.

Alternately, the Feedback Node automatically appears when you wire the output of a subVI, function, or group of subVIs or functions to the input of that same VI, function, or group.

Configure Feedback Nodes using the Properties dialog box, accessible when you right-click a Feedback Node and select Properties from the shortcut menu. If you place a checkmark in the Ignore FPGA reset method checkbox on the Configuration page of this dialog box, the LabVIEW FPGA Module removes the reset from the underlying register instantiations. This removal gives the compiler the option to implement the delays using shift register look-up tables (SRLs) instead of flip-flops. SRLs combine many delays into a single look-up table (LUT), which can reduce FPGA resource use significantly.

In loops, you can right-click a Feedback Node and select Replace with Shift Register from the shortcut menu to replace the Feedback Node with shift registers. You also can replace shift registers with a Feedback Node. However, you cannot implement shift registers using SRLs.

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