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To transfer data between different portions of an FPGA VI, between VIs on an FPGA target, or between devices, use a FIFO. A FIFO is a data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out access policy.
The following illustration demonstrates the behavior of elements moving through a FIFO.
Use FIFOs to transfer data in the following ways:
Use the FIFO Properties dialog box to create and configure FIFOs.
All FIFOs except VI-defined FIFOs have a corresponding item in the project. Therefore, if you use a FIFO other than a VI-defined FIFO and send the FPGA VI to another user, you must send the entire project. Otherwise, you cannot run the FPGA VI.
Use the following flow chart to determine the FIFO configuration that best fits your application needs.
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Note You can use the Target Information component on the General page of the FPGA Target Properties dialog box to get the number of block memory resources that an FPGA target supports. |
The following figure shows an example of a target-scoped FIFO used to transfer data between two single-cycle Timed Loops in the same FPGA VI. The single-cycle Timed Loops are in two different clock domains. The top loop uses an 80 MHz clock and the bottom loop uses a 40 MHz clock. In this example, an FPGA I/O Node in the 80 MHz clock domain acquires temperature readings from a device. A FIFO Method node writes the data to a FIFO. If the empty elements in the FIFO are not available for writing immediately, the node times out, stops the loop, and sets the Write Timed Out? indicator to TRUE. A FIFO Method node in the 40 MHz clock domain reads the data, then passes the data to a Less Than 0? function. If the temperature is less than zero, the function sets the Device Frozen? indicator to TRUE. If the data is not available to read immediately, the FIFO Method node times out, stops the loop, and sets the Read Timed Out? indicator to TRUE.
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Note If the FIFO Method Node contains a Timeout input parameter, you must wire a constant of zero to the parameter when the node is in a single-cycle Timed Loop. |
You can transfer data in the following ways:
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Note If you include multiple reads or writes to the same FIFO, the FIFO can become a shared resource. To prevent data corruption and jitter, avoid simultaneous read or write requests to a single FIFO. |
Choosing between the FIFO Implementation Options
Choosing between the FIFO Interface Options
Implementing Multiple Clock Domains
Using Peer-to-Peer Streaming with FPGA Targets
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