Unsupported LabVIEW Features (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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Restricted and Unavailable LabVIEW Features

  • ActiveX
  • Conditional loop tunnels
  • Dialog boxes
  • File I/O
  • Double-precision or extended-precision floating-point operations
  • For Loop iteration parallelism
  • Math and Signal Processing VIs not specific to the FPGA Module
  • Printing
  • Programmatic menus
  • Shared variables (except some targets that support the NI Scan Engine)
  • Arrays that do not resolve to a single size at compile time
  • Multidimensional arrays
  • VI Server
  • VI Server properties and methods

Support for other LabVIEW features varies by target.

Multidimensional Arrays or Arrays Unresolvable to a Single Size at Compile Time

You can use only one-dimensional arrays in FPGA VIs. LabVIEW must statically determine the size of an array at compile time. If necessary, you can make any array constant, control, or indicator fixed-size by right-clicking the array index and selecting Set Size from the shortcut menu. This option is only available in FPGA VIs.

LabVIEW must resolve arrays to a single size at compile time. This might mean that certain properties of the array, such as its length or the indexes of the elements you read/write, must be constant values. For example, if you use the Array Subset function, the index and length inputs must be constant so that LabVIEW can determine a set size for the output subarray. You can either wire constant values directly to array functions, or rely on value propagation through constant folding.

Tip  Because you can store large amounts of data in arrays on the FPGA, you can easily exceed the available FPGA resources. If you need to free FPGA resources, consider reducing the size of arrays in your FPGA application.

Shared Variables and the NI Scan Engine

Support for shared variables varies by FPGA target and RT controller. Not all CompactRIO RT controllers support the NI Scan Engine. Refer to the specific FPGA target or RT controller hardware documentation for more information about FPGA target and RT controller functionality.


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