|LabVIEW 2016 FPGA Module Help|
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You can place all High Throughput Math functions inside a single-cycle Timed Loop. However, be aware of the following caveats in this situation:
The High Throughput Add, Subtract, and To Fixed-Point functions are single-cycle functions. These functions execute in a single FPGA clock cycle. All other High Throughput Math functions are multi-cycle functions. These functions need more than one clock cycle to execute. If you place several multi-cycle functions in a single-cycle Timed Loop, the combinatorial path might become too long to execute in a single clock cycle.
For a multi-cycle High Throughput Math function in a single-cycle Timed Loop, you use the Throughput control, located in the configuration dialog box of that function, to specify the throughput rate you want the function to achieve. The throughput rate, in cycles/sample, is the minimum number of FPGA clock cycles that must elapse before this function can receive valid input data. Therefore, smaller values of the Throughput control mean the function can execute faster, because fewer clock cycles must elapse before the function is ready to receive valid input data.
|Note The Throughput value of a single-cycle function is always 1 cycle / sample.|
To demonstrate the importance of the Throughput control, consider three multi-cycle High Throughput Math functions connected by handshaking terminals. Within this series of three connected functions, the slowest throughput rate in that series (that is, the Throughput control with the highest value) is the fastest throughput rate that all connected functions can achieve. This limitation is true for each independent series of connected functions in a single-cycle Timed Loop.
|Note The Throughput control of a function is available only if you place that function inside a single-cycle Timed Loop. If you place the function outside a single-cycle Timed Loop, LabVIEW dims the Throughput control and displays a constant value of >1 call / sample. This value means the function can receive valid input data every time the VI calls the function.|
Although multi-cycle High Throughput Math functions execute during every clock cycle of a single-cycle Timed Loop, these functions do not return valid values during every cycle. You can configure these functions to display four handshaking terminals on the function icon. You use these terminals to determine when the following actions occur:
|Note Different functions have different criteria for determining whether the handshaking terminals appear. For example, the terminals appear on the High Throughput Divide icon when you select Inside single-cycle Timed Loop. To enable these terminals on the High Throughput Add function, you also must place a checkmark in the Register outputs checkbox.|
If you place several High Throughput Math functions inside a single-cycle Timed Loop, the length of the combinatorial path can prevent the FPGA VI from compiling at the necessary clock rate. In this situation, the Compilation Status window returns an error when you compile the FPGA VI. You can avoid these errors by increasing the number of pipelining stages or by adding input and/or output registers to the function.
You can reduce the length of the combinatorial path by placing the High Throughput Complex Multiply function or the High Throughput Multiply function inside a single-cycle Timed Loop and specify a large Number of pipelining stages. When you specify a large Number of pipelining stages, LabVIEW increases the chance that the function can compile at the necessary clock rate.
You also can reduce the length of the combinatorial path by adding registers for the inputs and/or outputs of a function. Adding registers can prevent compilation errors. However, each set of registers also increases the latency of the function by one cycle, which means you must wait an extra cycle to receive a valid output value.
|Note Some functions, such as the High Throughput Subtract function, support adding only one set of registers.|
The following figure shows how data flows through a function that contains these internal registers.
Use the Registers section of a configuration dialog box to add input and/or output registers.
|Note If you place a function outside a single-cycle Timed Loop, LabVIEW automatically places registers at the function outputs when you compile the VI.|