|LabVIEW 2016 FPGA Module Help|
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|LabVIEW 2020 FPGA Module Help|
Inputs and outputs (I/O) on FPGA targets allow you to connect the FPGA target to other devices. FPGA I/O resources are fixed elements of the FPGA targets that you use to transfer data among the different parts of the system. On some FPGA targets, FPGA I/O resources correspond to lines on front panel connectors, PXI backplanes, or RTSI connectors. On other FPGA targets, FPGA I/O resources are nodes inside FPGAs that connect the part of the FPGA designed by NI with the part of the FPGA you design through FPGA VIs. For component-level IP (CLIP), I/O resources are nodes inside FPGAs that connect CLIP with the FPGA VI. Each FPGA I/O resource has a specific type, such as digital or analog. An FPGA target might have multiple I/O resources of the same or different types. You can create FPGA I/O items, determine the I/O resources on the FPGA target that you want to use, and then assign unique names to the I/O resources you use.
|Note Refer to the specific FPGA target hardware documentation for information about supported features and I/O functionality on the FPGA target you use. Refer to Managing Shared Resources for information about arbitrating I/O resources.|
Resources translate physical quantities to or from a digital value that you manipulate in FPGA Module software. An I/O resource has one or more terminals for receiving or generating a physical quantity. Many I/O resources on FPGA targets have physical terminals to which you can directly connect elements of the system.
When the FPGA VI runs on the FPGA target, it performs I/O operations in hardware. For example, if you configure an FPGA I/O Node to read a digital line, the FPGA I/O Node reads the line and returns the result to the FPGA VI. Because FPGA VIs run on the FPGA, the VI can react to the input with the speed and determinism available in the FPGA target hardware.
You can put analog and digital inputs and outputs together in the same node on the block diagram. You can use target-specific properties and methods on the FPGA I/O items with the FPGA I/O Property Node and the FPGA I/O Method Node, respectively.
FPGA targets might organize digital I/O resources as individual lines or as groups of lines called ports. Some FPGA targets provide access to digital I/O resources exclusively as lines or ports. Other FPGA targets allow you to access the same physical lines both as individual lines and as ports. There are three types of digital I/O resources: those that read input, those that write output, and those that can perform both functions. Refer to the FPGA target hardware documentation for information about digital I/O support.
You can read digital input FPGA resources with the FPGA I/O Node. Use digital input resources to monitor circuitry outside the FPGA target.
You can write digital output FPGA resources with the FPGA I/O Node. Use digital output resources to control circuitry outside the FPGA target.
Some FPGA targets contain bidirectional, or tristate, digital I/O resources. In LabVIEW FPGA, tristate digital I/O resources are called digital input and output resources. You can read and write digital input and output resources with the FPGA I/O Node. You can use digital input and output resources to monitor and control circuitry outside the FPGA target. Tristate resources allow you to configure the I/O resource and control the direction of dataflow. Use the FPGA I/O Method Node configured with the Set Output Enable method to change the direction of dataflow. Wire a TRUE value to the Enable input to configure the tristate I/O resource as an output resource. Wire a FALSE value to the Enable input to configure the tristate I/O resource as an input resource.
|Note The default direction typically is input.|
As shown in the following illustration, an Output Enable signal controls whether the line is configured for input or output.
The tristate resource acts like a switch that the Output Enable signal controls, as shown in the following illustration.
When the Output Enable signal is TRUE or equal to 1, the digital line is configured as an output, and the value stored in Output Data will be driven on the digital line. When the Output Enable signal is FALSE or equal to 0, the digital line is configured as a high-impedance input allowing the line to be driven by an external device, as shown in the following illustration.
Regardless of the state of the Output Enable signal, you can use Input Data to monitor the current state of the digital line.
If you use an FPGA I/O Node to read a digital input and output resource, the FPGA I/O Node does not change the direction of the resource. If you use a digital input and output resource to write output, you must disable the output before you can use the same resource to read input. As shown in the following illustration, the FPGA I/O Method Node with the Set Output Enable method disables the output line before the FPGA I/O Node configured with a digital input and output resource reads the state of an external signal. Otherwise, the FPGA I/O Node simply reads back the last value written by the FPGA VI.
If you use the FPGA I/O Node to write a digital input and output resource, the FPGA I/O Node both writes the data and enables the terminal for output. You also can use the FPGA I/O Method Node with the Set Output Data method to write data without enabling the output. Use the FPGA I/O Method Node with the Set Output Enable method to enable the digital terminal, which allows the data to be driven out. Use the Set Output Data method before the Set Output Enable method to specify the state of the digital input and output resource when you enable the output. For example, you might have one portion of the block diagram continuously generating an internal signal. Use the FPGA I/O Method Node with the Set Output Enable method in another portion of the block diagram to independently control when the internal signal is actually driven out to an external device.
If you include a digital I/O resource in a single-cycle Timed Loop, each synchronization register introduces a delay corresponding to one iteration of the single-cycle Timed Loop. In some cases, delays outside the FPGA may be significant for the system. If accurate modeling of the delays between the LabVIEW diagram and the FPGA is important for testing the logic of the application by executing the FPGA VI on a development computer, delay simulation data for the I/O by the number of calls to the I/O node, equivalent to the number of synchronization registers.
If the FPGA target you use includes analog input resources, you can configure an FPGA I/O Node to read an analog input value. If you configure the FPGA I/O Node to read an analog input, the FPGA I/O Node might initiate a conversion, wait for the result, then return the binary representation of the voltage as a signed integer or fixed-point number. The analog input process and the resulting data type varies by FPGA target. For many FPGA targets, you create the FPGA VI to use the data returned by the analog input FPGA I/O Node for operations within the FPGA VI. You also can pass the data back to the host VI and, if applicable, convert the data to a voltage or other physical quantity if you have a transducer attached to the FPGA target analog input.
The equation you use to convert the binary representation to a physical quantity depends on the FPGA target and transducer. For example, with an NI PXI-7831R device, use the following equation to convert the binary representation to voltage: Input Voltage = (Binary Code / 32768) x 10.0V. Refer to the specific FPGA target hardware documentation for more information.
If the FPGA target you use includes analog output resources, you can configure an FPGA I/O Node to write an analog output value. If you configure the FPGA I/O Node to write an analog output, the FPGA I/O Node writes the binary representation of the voltage to the digital-to-analog converter (DAC), which sets the analog output voltage. The data type varies by FPGA target. You can generate voltage information from two sources—the host VI or the FPGA VI. Typically the host VI converts the voltage to an appropriate binary representation before writing the value to the FPGA VI. If the FPGA VI determines the voltage, typically the FPGA VI performs the calculations using the appropriate binary representations. In both cases, the DAC produces a voltage that corresponds to the binary representation.
The equation you use to convert a voltage to a binary representation depends on the specific FPGA target. For example, with an NI PXI-7831R device, use the following equation to convert the voltage to the binary representation: Binary Code = (Output Voltage x 32768) / 10.0V. Refer to the specific FPGA target hardware documentation for more information.