Using a Host VI to Communicate with the FPGA Target (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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You can programmatically interact with an FPGA VI using a separate VI running on the host computer. This programmatic FPGA interface communication differs from interactive front panel communication because it requires you to create a host VI as well as an FPGA VI.

When you use programmatic FPGA interface communication, the FPGA VI runs on the FPGA target, and the host VI runs on the host computer, as shown in the following illustration.

You use a host VI to send information between the host computer and the FPGA target for the following reasons:

  • You want to do more data processing than you can fit on the FPGA.
  • You need to perform operations not available on the FPGA target, such as double-precision or extended-precision floating-point arithmetic.
  • You want to create a multi-tiered application with the FPGA target as a component of a larger system.
  • You want to log data.
  • You want to control the timing and sequencing of data transfer.
  • You want to create a test bench for an FPGA VI.

The host computer can be a Windows-based computer or an RT target. Both the Windows OS and RT OS support the FPGA Interface functions. In addition, you can use the FPGA Interface functions on the RT target to communicate with the FPGA target and then use a Windows-based computer to communicate with the RT target.

Note  You cannot use the FPGA Interface functions on a Linux OS. Instead, use the FPGA Interface C API.

The following steps outline the general programming sequence for the host VI:

  1. Open a reference to an FPGA VI, build specification or bitfile.
  2. Send or receive data using the FPGA Interface functions, such as the Read/Write Control and Invoke Method functions.
  3. Close the FPGA reference with the Close FPGA VI Reference function.

The following block diagram shows a simple host VI that demonstrates this architecture. In this host VI, the application writes a value to the Boolean control, DIO1, on the FPGA and reads a value from the Boolean indicator, DIO0, on the FPGA.

The code in the While loop changes depending on your application and the way you transfer data between the FPGA and the host.


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