Using VHDL Code as Component-Level IP (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
View Product Info

DOWNLOAD (Windows Only)

LabVIEW 2015 FPGA Module Help
LabVIEW 2016 FPGA Module Help
LabVIEW 2017 FPGA Module Help
LabVIEW 2018 FPGA Module Help
LabVIEW 2019 FPGA Module Help

Use component-level IP (CLIP) to instantiate VHDL code with a defined interface that occupies a portion of an FPGA. You can use CLIP to perform the following tasks:

  • Run VHDL code in parallel with LabVIEW code.
  • Execute VHDL code in multiple clock domains.
  • Include constraints in the compilation.
  • Create CLIP clocks.
  • Access hardware I/O. (This is only available for some targets. Refer to the hardware documentation for information about I/O support in CLIP.)
Note  You must be familiar with VHDL to use CLIP.

Using CLIP in an FPGA Application

The following steps outline the procedure for using CLIP in an FPGA application:

Tip   If you create or modify a declaration XML file using the Configure Component-Level IP wizard, LabVIEW automatically adds the file to the project.

Types of CLIP

Support for CLIP varies by FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets support one or both of the following types of CLIP:

  • User-defined CLIP—Enables VHDL code to communicate directly with an FPGA VI.
  • Socketed CLIP—Enables VHDL code to communicate directly with an FPGA VI and to access FPGA pins that you cannot access with other LabVIEW VIs and functions. Some FPGA targets define a fixed CLIP socket in the FPGA where you can insert socketed CLIP.

The following illustration shows the relationship between an FPGA VI and CLIP.

Refer to the CLIP Tutorial: Adding Component-Level IP to an FPGA Project for an example of using VHDL code as CLIP.

WAS THIS ARTICLE HELPFUL?

Not Helpful