|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Use component-level IP (CLIP) to instantiate VHDL code with a defined interface that occupies a portion of an FPGA. You can use CLIP to perform the following tasks:
|Note You must be familiar with VHDL to use CLIP.|
The following steps outline the procedure for using CLIP in an FPGA application:
|Tip If you create or modify a declaration XML file using the Configure Component-Level IP wizard, LabVIEW automatically adds the file to the project.|
Support for CLIP varies by FPGA target. Refer to the target hardware documentation for information about CLIP support. Some FPGA targets support one or both of the following types of CLIP:
The following illustration shows the relationship between an FPGA VI and CLIP.
Refer to the CLIP Tutorial: Adding Component-Level IP to an FPGA Project for an example of using VHDL code as CLIP.