Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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LabVIEW automatically optimizes code inside a single-cycle Timed Loop (SCTL) to execute more quickly and consume less space on the FPGA target, compared to the same code inside a While Loop. When you use a While Loop with an FPGA target, the While Loop takes multiple clock cycles to execute each iteration because the While Loop includes the enable chain registers. The number of clock cycles that the While Loop takes for each iteration is dependent on the code inside the loop. When you use an SCTL with an FPGA target, the SCTL executes all functions inside the loop within a single clock cycle. Using the SCTL on FPGA targets reduces execution cycles and saves resources, mainly because the SCTL does not include the enable chain registers. If the SCTL contains initialized shift registers, it takes one clock cycle before the first iteration to initialize shift register values. The SCTL is similar to a clocked process in HDL.

The following block diagram illustrates the difference between the While Loop and SCTL in terms of executing the same code.

The following list describes important details about the previous diagram.

The code within the While Loop takes four clock cycles to execute, excluding the overhead of the While Loop, which takes two additional clock cycles to execute.
The red vertical lines indicate where each clock cycle ends inside the While Loop.
The same code in a SCTL executes within one clock cycle, if the clock period is long enough for the logic.

You can also include logic in a SCTL to optimize code by reducing execution cycles in an FPGA VI, as demonstrated in the following block diagram.

If you use a SCTL within a While Loop, as demonstrated in the previous diagram, wire a TRUE constant to the condition terminal so that the code within the Timed Loop executes only once per iteration of the While Loop.

Related Information

Timed Loop (Single-Cycle)

While Loop

Dataflow and the Enable Chain in FPGA VIs

Structures Palette Details

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