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NI exposes AXI, or Advanced eXtensible Interface, protocol for certain Xilinx IP on specific hardware targets. AXI protocol is an industry standard bus interface for interconnecting functional blocks of IP for high performance, high frequency applications. There are three types of AXI protocol: AXI4, AXI4-Lite, and AXI4-Stream.
|Note AXI protocol support in the LabVIEW FPGA Module varies by target family. The Xilinx IP Functions palette displays only IP that your FPGA device supports. Refer to the IP data sheet for information about interface and FPGA device support.|
The AXI protocol is similar to the LabVIEW four-wire handshaking protocol in the signal connections. The main difference between the AXI protocol and the LabVIEW four-wire handshaking protocol is signal naming and placement of Feedback Nodes when interconnecting IP in the single-cycle Timed Loop.
AXI signals in Xilinx IP follow a general naming convention for their input and output terminals: m/s + protocol + signal name + tdata/tvalid/tready, where m represents the master block, or the node that produces the value, and s represents the slave block, or the node that consumes the value. For example, in the signal name m_axis_signal_tvalid, m represents the master, axis represents AXI Stream, signal represents the signal name, and tvalid represents valid.
AXI signals in IP created by NI follow a naming convention similar to that of Xilinx IP, but omit the axis term: m/s + signal name + tdata/tvalid/tready.
The following sections show how to wire your IP depending on the interfaces involved.
The following diagram shows a conceptual configuration for the interconnection of two AXI4-Stream IP blocks.
The signals that flow downstream serve a similar purpose to those signals in the four-wire handshaking protocol. They inform downstream blocks of the validity of the data coming from the upstream block. For example, assuming two simple blocks with input signal x and output signal y, the m_y_tvalid output of IP Block 1 is TRUE whenever its m_y_tdata output contains valid y data.
The main difference between the LabVIEW four-wire handshaking protocol and the AXI Stream protocol lies in the meaning of the feedback signals, represented by the wires that flow upstream of the processing chain. An AXI signal informs upstream blocks of current cycle readiness and the four-wire signal informs upstream blocks of next cycle readiness. In AXI interfaces, a block deasserts its tready signal to indicate to its upstream counterpart that it is unable to receive data during the current clock cycle. The following timing diagram shows this scenario in the first few cycles. Notice that the value of tdata is held until the tready signal is reasserted.
The timing diagram above also shows how the master can halt the transfer by deasserting the tvalid signal in later cycles.
When interconnecting AXI IP in the single-cycle Timed Loop in LabVIEW, the output signals of IP Block 1 (AXI) connect to downstream IP Block 2 (AXI) through a Feedback Node, which acts as a register in the forward path. The Feedback Node temporarily stores any data in flight at the time the s_x_tready signal is deasserted until the slave block is ready to accept new data.
In AXI4-Stream, master blocks are not allowed to wait until the slave block is ready before producing valid data. When implementing blocks that conform to the AXI protocol, the block must repeatedly produce the same output, if valid, for as long as the associated tready signal remains deasserted. Additionally, an OR gate is needed to prime the handshaking process, as shown in the following diagram.
The four-wire to AXI interconnect is similar to the AXI to AXI interconnect in its use of registers. The following diagram shows how to connect a single signal of a four-wire IP block to an AXI IP block.
The AXI to four-wire interconnect is similar to the four-wire to four-wire interconnect in its use of registers, but requires an AND gate to conform to the four-wire protocol requirement of providing valid data only when the downstream block is ready for input, as shown in the following diagram.