Xilinx Options Page for Vivado (Compilation Properties Dialog Box)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

You can display this page in the following two ways:

  • If an FPGA build specification does not exist, right-click Build Specifications under an FPGA target in the Project Explorer window and select New»Compilation to display the Compilation Properties dialog box. Select Xilinx Options from the Category list to display this page.
  • If an FPGA build specification exists, right-click the build specification and select Properties from the shortcut menu to display the Compilation Properties dialog box. Select Xilinx Options from the Category list to display this page.
Note  Not all FPGA targets support the Xilinx Options page. If the target does not support this page, it does not appear in the Category list. Additionally, depending on your target, you may see the Xilinx Options Page for ISE (Compilation Properties Dialog Box).

Use this page to define the Xilinx Vivado options to use when you compile an FPGA VI. The options you can specify depend on your specific FPGA target. Refer to the support document at ni.com for more information about NI hardware supported by each Xilinx compilation tool.

In general, you do not need to adjust the options on this page unless the FPGA VI fails to compile. Use the information from the Compilation Status window to determine which options on this page might help the FPGA VI compile successfully. Refer to the Xilinx website at www.xilinx.com for information about different Vivado design strategies and directive options.

This page contains the following components:

  • Implementation strategy—Specifies a set of Xilinx options for the application. You can select from preset configurations to optimize performance, optimize the design area, optimize power, optimize design congestion on the chip, or reduce compilation time. You also can override any of the options of a design strategy to create a custom configuration.
    • Default—Configures the Xilinx compiler to use the Xilinx default implementation strategy.
    • Optimize performance—Selects the options that maximize the timing performance of the FPGA application.
    • Optimize area—Selects options that reduces LUT count on the FPGA chip.
    • Optimize power—Selects options that optimize the power usage on the FPGA chip.
    • Optimize congestion—Selects options that minimize design congestion on the FPGA chip.
    • Reduce compilation time—Selects options that minimize the compilation time by reducing the mapping effort of the Xilinx compiler.
    • Custom—Indicates that options might not match any of the preset configurations.
  • Design optimization directive—Specifies how the Xilinx compiler optimizes the FPGA design. This option is available only when you select the Custom option in Implementation strategy.

    You can choose Default, Explore, Explore area, Explore sequential area, Add re-map, Run-time optimized, or Disable BRAM power optimization.

    Refer to the Xilinx website at www.xilinx.com for more information about Vivado directive options.

  • Placement directive—Specifies how the Xilinx compiler places the FPGA design on the chip. This option is available only when you select the Custom option in Implementation strategy.

    You can choose Default, Explore, Wire-length-driven block placement, Late block placement, Extra net delay (high), Extra net delay (medium), Extra net delay (low), Spread logic (high), Spread logic (medium), Spread logic (low), Extra post-placement optimization, Extra timing optimization (SSI), Spread SSLs (SSI), Balance SSLs (SSI), Balance SLRs (SSI), High utilization SLRs (SSI), Run-time optimized, Quick, or Alternate wire-length-driven placement.

    Refer to the Xilinx website at www.xilinx.com for more information about Vivado directive options.

  • Physical design optimization directive—Specifies how the Xilinx compiler optimizes the FPGA design on the chip. This option is available only when you select the Custom option in Implementation strategy.

    You can choose Default, Explore, Explore with hold violation fixing, Aggressively explore, Alternate replication, Aggressive fan-out optimization, Alternate delay modeling, Add register re-timing, Alternate flow with re-timing, or Not enabled.

    Refer to the Xilinx website at www.xilinx.com for more information about Vivado directive options.

  • Routing directive—Specifies how the Xilinx compiler routes the FPGA design on the chip. This option is available only when you select the Custom option in Implementation strategy.

    You can choose Default, Explore, No timing relaxation, More global iterations, Higher delay cost, Advanced skew modeling, or Run-time optimized.

    Refer to the Xilinx website at www.xilinx.com for more information about Vivado directive options.

  • Run power optimization?—Specifies that the Xilinx compiler adds power optimization to reduce power consumption. By default this checkbox contains a checkmark only if you select the Optimize power option in Implementation strategy.
  • Build using multiple threads, if available—Specifies that the Xilinx compiler uses multithreading, if multiple threads are available. By default, this checkbox contains a checkmark.

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