FPGA CLIP Clock Properties Dialog Box

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Right-click a CLIP clock in the Project Explorer window and select Properties from the shortcut menu to display this dialog box.

Use this dialog box to rename a CLIP clock in the Project Explorer window and view the configuration of the CLIP clock. The dimmed components in this dialog box display the clock values from the CLIP declaration file. You cannot configure the CLIP clock in this dialog box. Instead, you must update the CLIP declaration file.

This dialog box includes the following components:

  • Name—Specifies the name of the clock that appears in the Project Explorer window.
  • Compile for single frequency—Indicates the frequency of the clock if the clock is not variable.
  • Compile for range of frequencies—Indicates that the FPGA VI has a range of clock frequencies.
  • Min Duty Cycle (% High)—Indicates the minimum percentage of time the clock remains high over one period.
  • Max Duty Cycle (% High)—Indicates the maximum percentage of time the clock remains high over one period.
  • Accuracy (ppm)—Indicates the accuracy of the clock in parts per million.
  • Peak Period Jitter (ps)—Indicates the maximum period jitter of the clock in picoseconds.
  • Supports and Requires Runtime Enable/Disable—Indicates whether you use the Start Enabling FPGA Clock and Start Disabling FPGA Clock Vis to enable and disable the clock. CLIP clocks do not support run time enabling and disabling.

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