LabVIEW 2018 FPGA Module Help
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Requires: FPGA Module
Use this page of the Configure Component-Level IP wizard to specify the CLIP declaration name and define the synthesis and simulation files the CLIP can use.
Click the Create File or Modify File button in the Component-Level IP page of the FPGA Target Properties dialog box to display this wizard.
This page includes the following components:
- Declaration name—Specifies the name of the CLIP declaration. This name is not the same as the name of the declaration XML file itself, which you will specify later in the wizard.
- Component-level IP description—Specifies a description to associate with the CLIP. You can view and edit the description on this page only.
- Synthesis File—Displays the synthesis files that compose the IP.
- Simulation Behavior—Displays the simulation behavior that corresponds to each synthesis file.
- Add Synthesis File—Prompts you for a synthesis file to add to the CLIP declaration. The files you add appear in the table under the Synthesis File column.
- Set Simulation Behavior—Launches the Set Simulation Behavior dialog box, which you use to change the simulation behavior of the selected synthesis file or exclude this synthesis file from simulation.
- Set as Top Level—Sets the selected synthesis file as the top-level file.
|Note CLIP does not support using a netlist file as the top-level synthesis file.|
- Remove—Removes the selected synthesis file from the table.