|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Requires: FPGA Module
Right-click an FPGA base, external, or CLIP clock in the Project Explorer window and select New FPGA Derived Clock from the shortcut menu to display this dialog box. You also can right-click an existing derived clock in the Project Explorer window and select Properties to display this dialog box.
Use the FPGA Derived Clock Properties dialog box to create and configure FPGA-derived clocks. You can scale the frequency of an FPGA target base, external, or CLIP clock by using a derived clock. If you do not know if the FPGA target supports the frequency you want to use, enter a value in the Desired Derived Frequency and read the resulting Message text. LabVIEW selects a supported clock using the equation in the Actual Derived Configuration and determines a Derived Frequency as close as possible to the Desired Derived Frequency.
Support for FPGA-derived clocks varies according to FPGA target.
This dialog box includes the following components: