FPGA Derived Clock Properties Dialog Box

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Right-click an FPGA base, external, or CLIP clock in the Project Explorer window and select New FPGA Derived Clock from the shortcut menu to display this dialog box. You also can right-click an existing derived clock in the Project Explorer window and select Properties to display this dialog box.

Use the FPGA Derived Clock Properties dialog box to create and configure FPGA-derived clocks. You can scale the frequency of an FPGA target base, external, or CLIP clock by using a derived clock. If you do not know if the FPGA target supports the frequency you want to use, enter a value in the Desired Derived Frequency and read the resulting Message text. LabVIEW selects a supported clock using the equation in the Actual Derived Configuration and determines a Derived Frequency as close as possible to the Desired Derived Frequency.

Support for FPGA-derived clocks varies according to FPGA target.

This dialog box includes the following components:

  • Name—Specifies the name of the derived clock that appears in the Project Explorer window below the parent clock.
  • Parent Clock Name—Displays the name of the parent clock from which the derived clock was created.
  • Desired Derived Frequency—Specifies the frequency you want the FPGA-derived clock to use.
  • Actual Derived Configuration—Displays the equation LabVIEW uses to determine the frequency of the derived clock. LabVIEW optimizes the derived configuration to use the least amount of resources on the FPGA.
    • Parent Frequency—Displays the frequency of the parent clock from which you derive the new clock.
    • Multiplier—Displays the numerator of the number by which LabVIEW multiplies the Parent Frequency to determine the derived frequency of the FPGA-derived clock.
    • Divisor—Displays the denominator of the number by which LabVIEW multiplies the Parent Frequency to determine the derived frequency of the FPGA-derived clock.
    • Derived Frequency—Displays the frequency of the resulting derived clock.
    • Parent Period—Displays the period of the parent FPGA clock.
    • Derived Period—Displays the period of the FPGA-derived clock.
  • Message—Displays information about the FPGA-derived clock.

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