LabVIEW 2018 FPGA Module Help
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Requires: FPGA Module
Click the Investigate Timing Violation button in the Compilation Status window to display the Timing Violation Analysis window. The Investigate Timing Violation button appears only if the compile server encounters timing violations while trying to compile an FPGA VI.
Use this window to identify components in the FPGA application that cannot execute within the application clock rate. Double-click an item in the list or click the Show Element button to locate the node on the block diagram. You can use different strategies to fix timing violations.
This window includes the following components:
- Timing Information—Lists the propagation delay and maximum fanout of components in the FPGA VI that cause the timing violation. The units of Total Delay, Logic Delay, and Routing Delay are in nanoseconds.
- Paths—Lists sets of VIs and components that exceed the applicable FPGA clock rate. Each path describes the VIs and components between two internal registers.
When items in the table correspond to objects on the block diagrams, such as functions, structures, and subVIs, double-clicking the items in the table highlights the corresponding object on the block diagram.
Some items in the table are non-diagram components and do not correspond directly to objects on the block diagrams. Non-diagram components include resources, arbitration circuits, component-level IP (CLIP), and other circuits that depend on the target hardware. You may be able to use the internal name of the non-diagram component to correlate the non-diagram component with a block diagram object or CLIP. For specific FPGA targets, you can double-click a CLIP in the table to see the signal from the top category of the CLIP on the block diagram.
- Total Delay—Indicates the sum of Logic and Routing. Because of rounding, the value of Total might differ slightly from the sum of the values of Logic and Routing.
- Logic Delay—Indicates the amount of time in nanoseconds that a logic block takes to execute.
- Routing Delay—Indicates the amount of time in nanoseconds that a signal takes to traverse between FPGA logic blocks.
- Max Fanout—Displays the maximum number of logic block inputs from which a single logic block output connects. This maximum fanout can occur anywhere along the path. High signal fanout contributes to greater routing delays.
- Show Element—Highlights on the block diagram the item you select in the Paths list. You also can double-click an item in the Paths list to highlight the item on the block diagram.
- Show Path—Highlights on the block diagram all items in the path you select in the Paths list.
Erroneously Listed Single-Cycle Timed Loops
If the FPGA VI uses a large area on the FPGA, the Xilinx compiler optimizations might map different single-cycle Timed Loops to different look-up tables (LUTs) in the same slice. If two different single-cycle Timed Loops map to the same slice and a timing error occurs in one of them, the Timing Violation Analysis window might indicate the wrong single-cycle Timed Loop has the timing violation.