Top-Level Clock Page (FPGA Target Properties Dialog Box)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Requires: FPGA Module

Right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box. Select Top-Level Clock from the Category list to display this page.

Use this page to set the top-level clock of the FPGA target. Supported top-level clocks vary according to FPGA target.

This page includes the following components:

  • Default—Specifies that the top-level clock of the FPGA target is the default target base clock.
  • Select Configured Clock—Allows you to select a clock other than the default FPGA target clock as the top-level clock. Select from existing clocks included with the target or derived clocks you create.
  • Configured Clocks—Displays the list of available clocks you can set as the top-level FPGA target clock. You can select a clock in this list if you click the Select Configured Clock option.
    Note  You cannot select a clock that can be disabled as a top-level clock because the clock might prevent execution of the FPGA VI. Therefore, you cannot select an external clock as a top-level clock. You also cannot select a clock that must be enabled and disabled at run time.
  • Selection—Displays information about the top-level clock and if the FPGA target supports the clock you want to use.

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