|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
Requires: FPGA Module
Right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box. Select Top-Level Clock from the Category list to display this page.
Use this page to set the top-level clock of the FPGA target. Supported top-level clocks vary according to FPGA target.
This page includes the following components:
|Note You cannot select a clock that can be disabled as a top-level clock because the clock might prevent execution of the FPGA VI. Therefore, you cannot select an external clock as a top-level clock. You also cannot select a clock that must be enabled and disabled at run time.|