Using FPGA Clocks and Timing (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
View Product Info

DOWNLOAD (Windows Only)

---

	LabVIEW 2016 FPGA Module Help
	LabVIEW 2017 FPGA Module Help
	LabVIEW 2018 FPGA Module Help
	LabVIEW 2019 FPGA Module Help
	LabVIEW 2020 FPGA Module Help

You can use the following clocks in an FPGA application:

• Base clock—A digital signal existing in the target hardware that you can use as a clock for an FPGA application.
• Derived clock—A clock you create from a base clock that you can use as a clock for an FPGA application. You can scale the frequency of an FPGA target base, external, or CLIP clock by using a derived clock.
• Top-level clock—The global clock that the FPGA VI uses outside a single-cycle Timed Loop.

LabVIEW uses the base clock properties when setting timing constraints on circuits generated from the FPGA VI during compilation.

Every VI or function you place in an FPGA VI takes a certain amount of time, known as logic delay, to execute. The top-level clock on an FPGA target determines the execution time of the individual functions and VIs on the FPGA VI block diagram. If you change the frequency of the top-level clock, you also change the execution speed of functions on the block diagram and the execution rate of the FPGA VI.

By controlling the execution rate of the FPGA VI, you specify the timing objectives of an FPGA application. Operations occur at the rate determined by the dataflow of the VI if you do not include additional programming. To control or measure the execution timing, use the Timing VIs. You also can use the Timing VIs to create custom I/O applications, such as counters and triggers.

Related Information

Timed Loop (Single-Cycle)

Understanding Timing Considerations for FPGA VIs

Timing VIs

Creating FPGA-Derived Clocks

Selecting a Top-Level Clock for an FPGA Target

Controlling the FPGA VI Execution Rate