Creating FPGA-Derived Clocks (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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You can derive additional clocks from FPGA base clocks in a LabVIEW project. Complete the following steps to derive an FPGA clock.

Note  Support of FPGA-derived clocks varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.
  1. Create a new project or open an existing project.
  2. Add an FPGA target to the project.
  3. If the FPGA target you use does not automatically add the FPGA base clock you want to the Project Explorer window, add the FPGA base clock.
  4. Right-click an FPGA base clock in the Project Explorer window and select New FPGA Derived Clock from the shortcut menu. The FPGA Derived Clock Properties dialog box appears.
    Note   If the FPGA target does not support FPGA-derived clocks or the FPGA base clock you add, the New FPGA Derived Clock option is dimmed in the shortcut menu.
  5. (Optional) Enter a name in the Name text box. By default, the name is the actual derived frequency.
  6. Type the frequency at which you want the derived clock to run in the Desired Derived Frequency text box.

    LabVIEW finds the closest frequency that the underlying FPGA supports and displays it in the Derived Frequency text box in the Actual Derived Configuration section. If the FPGA supports the Derived Frequency, the Message text box displays that the frequency is available. Otherwise, it displays the error between the derived frequency and the desired frequency.
  7. Click the OK button to accept the derived frequency and close the dialog box. The FPGA-derived clock appears in the Project Explorer window with the derivation ratio in parentheses.

You now can set the new derived clock as the top-level clock in the project.


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