![]() | LabVIEW 2016 FPGA Module Help |
![]() | LabVIEW 2017 FPGA Module Help |
![]() | LabVIEW 2018 FPGA Module Help |
![]() | LabVIEW 2019 FPGA Module Help |
![]() | LabVIEW 2020 FPGA Module Help |
You can derive additional clocks from FPGA base clocks in a LabVIEW project. Complete the following steps to derive an FPGA clock.
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Note Support of FPGA-derived clocks varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information. |
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Note If the FPGA target does not support FPGA-derived clocks or the FPGA base clock you add, the New FPGA Derived Clock option is dimmed in the shortcut menu. |
You now can set the new derived clock as the top-level clock in the project.
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