Debugging FPGA VIs Using a Xilinx Simulator (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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The following procedure describes how to debug an FPGA VI using a Xilinx simulator and a VHDL test bench template that you edit.

  1. Configure LabVIEW to work with a Xilinx simulator.
  2. Modify the FPGA VI if necessary. For example, you might want to reduce the simulation run time.
  3. Right-click the FPGA target in the Project Explorer window and select Select Execution Mode»Third-Party Simulation from the shortcut menu.
  4. Create a simulation export build specification.
  5. Click the Build button in the Simulation Export Properties dialog box to build the simulation export.
    LabVIEW creates the files necessary for simulation and places them in the simulation directory.
  6. Provide the stimulus and response you want by modifying the VHDL code in the template.
  7. In the Project Explorer window, right-click the simulation export and select Launch Simulator to open the simulator project.
  8. Click the Run All button to run the simulation.
  9. View the signals in the waveform viewer and troubleshoot the FPGA VI. Make changes to the FPGA VI if necessary.
  10. Integrate the changes into the test bench if necessary.
  11. Run RegenerateIsim.bat, located in the user directory, to regenerate the simulation executable.
  12. Repeat steps 6 through 11 to continue troubleshooting the FPGA VI.

Related Information

Configuring LabVIEW for a Third-Party Simulator

Reducing Simulation Run Time

Debugging FPGA VIs Using Third-Party Simulation

Viewing Signals Using the Waveform Viewer

Integrating Changes to the VHDL Test Bench

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