LabVIEW 2018 FPGA Module Help
View Product Info
DOWNLOAD (Windows Only)
The following procedure describes how to debug an FPGA VI using a Xilinx simulator and a VHDL test bench template that you edit.
- Configure LabVIEW to work with a Xilinx simulator.
- Modify the FPGA VI if necessary. For example, you might want to reduce the simulation run time.
- Right-click the FPGA target in the Project Explorer window and select Select Execution Mode»Third-Party Simulation from the shortcut menu.
- Create a simulation export build specification.
- Click the Build button in the Simulation Export Properties dialog box to build the simulation export.
LabVIEW creates the files necessary for simulation and places them in the simulation directory.
- Provide the stimulus and response you want by modifying the VHDL code in the template.
- In the Project Explorer window, right-click the simulation export and select Launch Simulator to open the simulator project.
- Click the Run All button to run the simulation.
- View the signals in the waveform viewer and troubleshoot the FPGA VI. Make changes to the FPGA VI if necessary.
- Integrate the changes into the test bench if necessary.
- Run RegenerateIsim.bat, located in the user directory, to regenerate the simulation executable.
- Repeat steps 6 through 11 to continue troubleshooting the FPGA VI.
Configuring LabVIEW for a Third-Party Simulator
Reducing Simulation Run Time
Debugging FPGA VIs Using Third-Party Simulation
Viewing Signals Using the Waveform Viewer
Integrating Changes to the VHDL Test Bench