LabVIEW 2018 FPGA Module Help
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This topic describes how to set up and configure a compile farm. A compile farm consists of an on-site compile server and one or more on-site compile workers that multiple developers can target.
The following figure and description explain how the development computer, the compile server, and the compile workers operate together to deploy an FPGA VI to an FPGA target.
|You, or other developers, create an FPGA VI on a development computer and click the Run button in LabVIEW.|
|LabVIEW submits the compile job to the compile server.|
|The compile server sends the compile job to an available compile worker, which compiles the FPGA VI.|
|The compile worker submits the compiled VI back to the compile server.|
|The compile server submits the compiled VI back to the development computer. The FPGA VI is ready to deploy to the FPGA target.|
Understanding the LabVIEW FPGA Compile System
NI LabVIEW FPGA Compilation Options
Compiling an FPGA VI Remotely
Hardware and Software Requirements and Recommendations
NI recommends a compile farm setup with at least two computers: a compile server and a compile worker. The following table describes these computers and the development computer.
||Required Hardware and Software
||The computer(s) on which you develop FPGA VIs.
Each computer on which you develop FPGA VIs must include the following software:
- LabVIEW FPGA Module
- NI-RIO driver software
The computer that distributes compile jobs among the compile workers. You also log in to the compile server to configure user access to the compile farm and to manage compile jobs.
For maximum performance, NI recommends dedicating one computer to the compile server. Also, consider taking reliability precautions, such as using an uninterruptible power supply (UPS), to avoid the compile server failing. If the compile server fails, the compile workers abort any compile jobs in progress.
FPGA Compile Farm Server
Compile Farm Server automatically installs locally when you install the LabVIEW
FPGA Module. You must install the FPGA Compile Farm Server separately on any
computer that you want to use as a remote compile server.
Refer to the FPGA Module installation options on the Platform media for more information about installing the FPGA Compile Farm Server.|
||The computer(s) that compile FPGA VIs.
Each computer on which you compile FPGA VIs must include the following:
- Xilinx Compilation Tools for Windows or Xilinx Compilation Tools for Linux
- For Virtex-5 and earlier FPGAs—32-bit OS, 2–3 GB of RAM
- For Virtex-6 and later FPGAs—64-bit OS, 4–12 GB of RAM
To reduce compile times, NI recommends adding as much RAM as possible. Only 64-bit OSes can access 4 GB of RAM or more.
Setting up a Compile Farm
Before proceeding, identify the computer(s) that serve each role discussed in the table and ensure that you connect all computers across a network. Then, complete the following steps to set up the compile server, each compile worker, and the development computer(s).
Setting up the Compile Server
Complete the following tasks to set up the compile server.
- Install the FPGA Compile Farm Server on the computer you want to designate as the compile server. Make note of the IP address or hostname of this computer.
- Log in to the compile server.
- From a computer on the same network as the compile server, open a Web browser and navigate to http://<computername>:3580, where <computername> is the IP address or hostname of the compile server you recorded earlier. The compile server displays the NI Web-based Monitoring & Configuration service System Configuration page. Use this service to monitor and manage compile jobs in the queue.
- Click Login.
- Enter a user name and password that has administrative access to the NI Web-based Configuration & Monitoring service. By default, this user name is admin and the password is blank.
NI recommends securing the compile server as soon as possible. Refer to the Securing a Target section of the FPGA Compile Farm Console Help, available by clicking Help on the Security Configuration page, for information about this task.
If you access the compile server from the compile server itself, you do not need to log in.
- Configure users who can use the compile farm to compile FPGA VIs.
- Click the Security Configuration button .
- Add user names and assign them passwords by using the + button at the bottom of the Users tab. Only users listed on this tab can use the compile farm.
Refer to the Adding and Removing Users section of the console help, available by clicking Help, for more information adding users.
- Assign one or more users to the administrators group. Users in this group can compile FPGA VIs by using the compile farm, but also can manage the compile job queue, cancel compile jobs, show and hide compile workers, and so on.
Refer to the Assigning Users to a Group or Removing Users from a Group section of the console help, available by clicking Help, for information about assigning users to the administrators group.
- After you finish adding users and administrators, click Save and close the Web browser.
Setting up the Compile Workers
The next step is to make the compile server aware of each compile worker. For each compile worker, complete the following steps:
- Install the Xilinx compilation tools on any computer that you want to designate as a compile worker.
- Configure the compile worker.
- Start the compile worker by selecting Start»All Programs»National Instruments»FPGA»FPGA Compile Worker. Windows displays the LabVIEW FPGA Compile Worker icon in the taskbar.
- Double-click this icon to display the status and capabilities of the compile worker.
- Click Configure to configure the compile worker.
- Select Connect to a compile server.
- Enter the following information:
- Hostname: <computername>:3580, where <computername> is the IP address or hostname of the compile server.
- Username: admin
- Password: The password associated with the admin username. By default, this password is blank.
- Enter the Number of simultaneous jobs, which is the number of simultaneous compile jobs this worker can handle. Generally, one CPU core can handle one compile job. However, NI recommends leaving one core free for OS tasks. For example, if you have a quad-core CPU, NI recommends setting Number of simultaneous jobs to 3.
- Click OK.
- Verify that the compile server sees each compile worker.
- Log in to the compile server.
- Click the LabVIEW FPGA Compile Farm Console button .
- Verify that the compile workers you added appear in Workers list. You might have to adjust the filters to see the compile worker.
Setting up the Development Computer(s)
Configure development computers to compile FPGA VIs using the compile farm. For each development computer, complete the following steps:
- Install LabVIEW, the FPGA Module, and the NI-RIO driver software.
- Launch LabVIEW and select Tools»Options to display the Options dialog box.
- Select FPGA Module from the Category list.
- Locate the Compile Server section and select Connect to a compile server.
- In the dialog box that appears, click the + button to add a server.
- Enter <computername>:3580, where <computername> is the IP address or hostname of the compile server, in the Host name text box and click OK.
- Enter a User name and Password that you configured when you set up the compile server.
- Click Test Connection to test the connection between the development computer and the compile server. Fix any errors that occur.
- Click OK.