Using CLIP Clocks (FPGA Module)

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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You can instantiate clock circuitry in component-level IP (CLIP) and use CLIP clocks in the same way you use other clocks that the target provides. You also can route external clocks supplied by socketed CLIP to LabVIEW. CLIP clocks cannot be top-level clocks. Any clocks in the CLIP declaration file appear automatically under the CLIP item in the Project Explorer window.

You cannot use the Start Enabling FPGA Clock and Start Disabling FPGA Clock VIs with CLIP clocks to protect circuitry when the clock might not be available.

Including Clocks in the VHDL File

To ensure the CLIP clock uses a low-skew global clock net, you must use a global clock buffer (BUFG). NI recommends using a global clock buffer with gated input (BUFGCE) to ensure that the clock is disabled whenever the clock has glitches or violates the period constraint for the clock. Refer to the Xilinx documentation for information about creating a clock in VHDL.

Refer to the example of VHDL code for a CLIP clock for a demonstration of creating a clock in VHDL code.

Including Clocks in the CLIP Declaration File

You define a clock in the CLIP declaration file using the same syntax as defining I/O. The order that clock and I/O appear in the declaration file dictates the order in which they appear in the LabVIEW project. For the CLIP clock, you must define the following tags.

  • JitterInPicoSeconds
  • AccuracyInPPM
  • DutyCyclePercentInMin/Max

Use the Configure Component-Level IP wizard (CLIP wizard) to define the IP interface without editing the declaration XML file by hand.

Note Note  If you are using the Xilinx Digital Clock Manager (DCM) circuits to derive the CLIP clock, use the Xilinx specification sheets for the FPGA target to make sure you correctly configure the CLIP clock in the CLIP declaration file. The following table indicates where you can find the information for the specific declaration items.

CLIP Declaration TagType of Xilinx DocumentSuggested Search Terms to Find Information
JitterInPicoSecondsDC and Switching CharacteristicsOutput Clock Jitter
AccuracyInPPMDC and Switching CharacteristicsOutput Clock Phase Alignment
DutyCyclePercentInMin/MaxUser GuideDCM attributes

Adding CLIP Clocks to a LabVIEW Project

Complete the following steps to add a CLIP clock to a LabVIEW project.

  1. Create a new project or open an existing project.
  2. Add an FPGA target to the project.
  3. Add a CLIP item to the project..
  4. (Optional) Right-click the CLIP clock under the CLIP item in the Project Explorer window and select Properties from the shortcut menu to display the FPGA CLIP Clock Properties dialog box.
  5. (Optional) Rename the clock in the Name text box.

    All other components in the dialog box are dimmed but show the values of the CLIP clock. You cannot configure the CLIP clock from LabVIEW. You must update the CLIP clock in the CLIP declaration file to change the clock configuration.
  6. Click the OK button.

Deriving Clocks from CLIP Clocks

You can derive clocks from CLIP clocks. You must configure the CLIP clock to compile at a single frequency to enable the option to create a new derived clock.

Complete the following steps to derive a clock from an external clock:

  1. Follow the instructions above to add a CLIP clock to the LabVIEW project.
  2. Right-click the CLIP clock in the Project Explorer window. From the shortcut menu, select New FPGA Derived Clock to display the FPGA Derived Clock Properties dialog box.
  3. Configure the clock.
  4. Define the following tags in the CLIP declaration XML file file:
    • SupportDerivedClocks
    • SourceClockReadyHDLName
    • DerivedClocksValidHDLName

Using CLIP Clocks in SubVIs

You can use the clock constant or clock control to reference a CLIP clock in a subVI.

The name of the clock in the control or constant must match the name of the clock in the Project Explorer window exactly. If the names do not match, you receive an error message when you compile the FPGA VI. Use the pull-down menu of the FPGA clock constant or control to ensure the clock name you specify matches the name of the clock in the project.

Accessing CLIP I/O Using a Different Clock than the CLIP Clock

You must consider clock domains when using CLIP I/O in a single-cycle Timed Loop using a different clock than the CLIP clock. If the CLIP executes in one clock domain and the FPGA VI accesses the corresponding CLIP I/O using a different clock domain, the signals can transfer between clock domains incorrectly. If this happens, the Timing Violation Analysis window displays a timing violation.

To avoid transferring data between clock domains incorrectly, use one of the following strategies.


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