|LabVIEW 2016 FPGA Module Help|
|LabVIEW 2017 FPGA Module Help|
|LabVIEW 2018 FPGA Module Help|
|LabVIEW 2019 FPGA Module Help|
|LabVIEW 2020 FPGA Module Help|
You can instantiate clock circuitry in component-level IP (CLIP) and use CLIP clocks in the same way you use other clocks that the target provides. You also can route external clocks supplied by socketed CLIP to LabVIEW. CLIP clocks cannot be top-level clocks. Any clocks in the CLIP declaration file appear automatically under the CLIP item in the Project Explorer window.
To ensure the CLIP clock uses a low-skew global clock net, you must use a global clock buffer (BUFG). NI recommends using a global clock buffer with gated input (BUFGCE) to ensure that the clock is disabled whenever the clock has glitches or violates the period constraint for the clock. Refer to the Xilinx documentation for information about creating a clock in VHDL.
Refer to the example of VHDL code for a CLIP clock for a demonstration of creating a clock in VHDL code.
You define a clock in the CLIP declaration file using the same syntax as defining I/O. The order that clock and I/O appear in the declaration file dictates the order in which they appear in the LabVIEW project. For the CLIP clock, you must define the following tags.
Use the Configure Component-Level IP wizard (CLIP wizard) to define the IP interface without editing the declaration XML file by hand.
|Note If you are using the Xilinx Digital Clock Manager (DCM) circuits to derive the CLIP clock, use the Xilinx specification sheets for the FPGA target to make sure you correctly configure the CLIP clock in the CLIP declaration file. The following table indicates where you can find the information for the specific declaration items.
Complete the following steps to add a CLIP clock to a LabVIEW project.
You can derive clocks from CLIP clocks. You must configure the CLIP clock to compile at a single frequency to enable the option to create a new derived clock.
Complete the following steps to derive a clock from an external clock:
The name of the clock in the control or constant must match the name of the clock in the Project Explorer window exactly. If the names do not match, you receive an error message when you compile the FPGA VI. Use the pull-down menu of the FPGA clock constant or control to ensure the clock name you specify matches the name of the clock in the project.
You must consider clock domains when using CLIP I/O in a single-cycle Timed Loop using a different clock than the CLIP clock. If the CLIP executes in one clock domain and the FPGA VI accesses the corresponding CLIP I/O using a different clock domain, the signals can transfer between clock domains incorrectly. If this happens, the Timing Violation Analysis window displays a timing violation.
To avoid transferring data between clock domains incorrectly, use one of the following strategies.