Selecting an FPGA Clock as the Timing Source for SCTLs (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Complete the following steps to select an FPGA base clock or derived clock as the timing source for a single-cycle Timed Loop (SCTL) in an FPGA VI. The SCTL uses the top-level clock of the FPGA target by default.

Note  Support of the single-cycle Timed Loop varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.
  1. Create a new project or open an existing project.
  2. Add an FPGA target to the project.
  3. If the FPGA target you use does not automatically add the FPGA base clock you want to the Project Explorer window, add the FPGA base clock. If you want to use the FPGA base clock as the timing source for the single-cycle Timed Loop, skip the following step.
  4. (Optional) Create an FPGA-derived clock.
  5. Create a new VI or open an existing VI under an FPGA target in the Project Explorer window.
  6. Add a Timed Loop to the block diagram.

  7. Select a clock by double-clicking the Input Node of the Timed Loop to display the Configure Timed Loop dialog box and selecting one of the following options:
    • Top-Level Timing Source—Select this option if you want the Timed Loop to inherit the top-level timing source of the project it is in. You might use this option if you intend to reuse an FPGA VI on multiple FPGA targets.
    • Select Timing Source—Select this option if you want to use a timing source in the project other than the top-level clock. Then select a timing source from the Available Timing Source list. To use a clock that is not in the list, create a new base clock or create a new derived clock.
    Alternatively, you can write reusable code by wiring an FPGA clock control to the Source Name input of the Timed Loop.

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