Generating Interrupts on the FPGA (FPGA Module)

LabVIEW 2018 FPGA Module Help


Edition Date: March 2018
Part Number: 371599P-01
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Some FPGA targets allow you to generate interrupts from the FPGA VI to notify the host VI of events, such as data being ready, an error occurring, or a task finishing. To determine whether a target supports interrupts, access the FPGA Target Properties dialog box and locate the Target Information section of the General page.

Note  You cannot use the Interrupt VI in a Timed Loop in an FPGA VI. You instead can use a Set Occurrence function in the Timed Loop and a Wait on Occurrence function in a separate While Loop. You then can use the Interrupt VI in the While Loop to generate an interrupt whenever an occurrence takes place.

Complete the following steps to generate interrupts in an FPGA VI.

  1. Add the Interrupt VI to the block diagram of the FPGA VI in the data flow where you want the FPGA VI to generate the interrupt for the host VI.

  2. Right-click the IRQ Number input of the Interrupt VI and select Create»Constant from the shortcut menu. You also can create a control or wire the output of another diagram node to the Interrupt VI input.
  3. Enter the value of the logical interrupt you want to use in the IRQ Number input. The value of the logical interrupt allows the host computer to distinguish between multiple interrupts set in the FPGA VI. If you set only one interrupt in the FPGA VI, you can use any logical interrupt number.
  4. Right-click the Wait Until Cleared input of the Interrupt VI and select Create»Constant from the shortcut menu.
  5. Set the Wait Until Cleared Boolean constant to TRUE if you want the Interrupt VI to wait until the host VI acknowledges the interrupt. Set the Wait Until Cleared Boolean constant to FALSE if you do not need the Interrupt VI to wait until the host VI acknowledges the interrupt.

Refer to Synchronizing FPGA VIs and Host VIs Using Interrupts for information about using interrupts in the FPGA Interface.

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