Sample Rate To Loop Time VI

LabVIEW 2018 FPGA Module Help

Edition Date: March 2018
Part Number: 371599P-01
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Owning Palette: Scaling VIs

Requires: FPGA Interface

Converts the desired sample rate to the appropriate count for the Loop Timer Express VI and computes the achievable sample rate for use with other Scaling VIs.

Use the pull-down menu to select an instance of this VI.

Sample Rate To Loop Time (ticks)

	FPGA clock rate (Hz) specifies the clock rate at which the compilation tools compile the FPGA VI.
	sample rate (S/s) specifies the sampling rate for the signal in samples per second.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	count (ticks/S) returns the time between loop iterations in units of clock cycles. The clock rate for the FPGA VI determines the length of time between iterations.
	actual sample rate (S/s) returns the achievable sampling rate based on FPGA clock rate (Hz).
	error out contains error information. This output provides standard error out functionality.

Sample Rate To Loop Time (us)

	FPGA clock rate (Hz) specifies the clock rate at which the compilation tools compile the FPGA VI.
	sample rate (S/s) specifies the sampling rate for the signal in samples per second.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	count (us/S) returns the time between loop iterations in microseconds.
	actual sample rate (S/s) returns the achievable sampling rate based on FPGA clock rate (Hz).
	error out contains error information. This output provides standard error out functionality.

Sample Rate To Loop Time (ms)

	FPGA clock rate (Hz) specifies the clock rate at which the compilation tools compile the FPGA VI.
	sample rate (S/s) specifies the sampling rate for the signal in samples per second.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	count (ms/S) returns the time between loop iterations in milliseconds.
	actual sample rate (S/s) returns the achievable sampling rate based on FPGA clock rate (Hz).
	error out contains error information. This output provides standard error out functionality.