IO Module Clock Selections Properties Page

In the Component-Level IP Properties dialog box, select Clock Selections from the Category list to display this page.

Use this page to link each clock port defined by the CLIP to a clock on the FPGA target. You must add the FPGA clock to the LabVIEW project before you can link to the FPGA clock.

This page includes the following components:

• Component-Level IP Clock—Lists clock(s) you defined in the CLIP declaration XML file.
• Connection—Lists clocks available on the FPGA target.