NI 6584 Channel CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides read/write access to all RS-485/422 channels using a simple channel-based interface. This CLIP has 16 data output lines, 16 data input lines, 16 data output enable lines, one clock I/O, one clock output enable, one PFI I/O, and one PFI output enable. This CLIP also allows for clock output inversion. The input lines are always enabled. In the LabVIEW FPGA Module, each input, output, enable, and PFI line is accessed using a Boolean signal.

This CLIP allows you to import or export a clock using the Clock BNC connector. When exporting an FPGA-generated clock, it can be inverted before it is generated. Inverting this clock allows you to synchronize the output data to either the rising or falling edge of the clock. Setting the Clock_Out_Invert signal to FALSE synchronizes the data with the rising edge, and setting the Clock_Out_Invert signal to TRUE synchronizes the data with the falling edge. A clock can also be imported on RX_0 if that channel is not used as a data line. To use RX_0 as a clock, add IOModuleCLIPClock0 to your LabVIEW FPGA project.

Example Projects

FlexRIO support installation includes a variety of example projects to help get you started with the NI 6584 Basic Channel CLIP. To access these examples in NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules»NI 6584.

Note  This folder contains examples for full duplex, full duplex no termination, half duplex, and half duplex no termination devices. Depending on your version of the NI 6584, select the appropriate examples for your device.

The following example projects use the I/O signals exposed by the NI 6584 Basic Channel CLIP:

  • Full Duplex
    • NI 6584 Basic Software UART Full Duplex - NoTerm.lvproj—This example implements the basic functionality of a UART (universal asynchronous receiver/transmitter). It can generate and receive data from basic UART (no flow control). The default channel for this UART to run is Channel 0.
    • NI 6584 Basic Software UART Full Duplex.lvproj—This example implements the basic functionality of a UART. It can generate and receive data from basic UART (no flow control). The default channel for this UART to run is Channel 0.
    • NI 6584 Finite Acquisition with External Clk-NoTerm (Full Duplex).lvproj—This example acquires a finite number of samples using an external clock and passes the data to the host VI through an Acquisition FIFO.
    • NI 6584 Finite Acquisition with External Clock (Full Duplex).lvproj—This example acquires a finite number of samples using an external clock and passes the data to the host VI through an Acquisition FIFO.
    • NI 6584 Finite Generation and Exported Clock (Full Duplex).lvproj—This example generates a finite number of parallel samples and exports the onboard clock to the Clock BNC connnector on the NI 6584. The example also outputs a data active signal on the PFI BNC connector while data is being generated. It uses a Generation FIFO to pass an array of samples from the host to the target to be generated.
    • NI 6584 Finite Generation Exported Clk-NoTerm (Full Duplex).lvproj—This example generates a finite number of parallel samples and exports the onboard clock to the Clock BNC connnector on the NI 6584. The example also outputs a data active signal on the PFI BNC connector while data is being generated. It uses a Generation FIFO to pass an array of samples from the host to the target to be generated.
    • NI 6584 Static Generation and Acquisition (Full Duplex).lvproj—This example demonstrates how to generate and acquire a static pattern from the NI 6584. Static generation places a single pattern on the configured lines. Static acquisition samples the configured channels once, returning data as a Boolean array. Both static generation and acquisition are controlled by software and do not use status signals or hardware timing. The FPGA continuously generates and acquires data, but the host VI determines the rate at which the device reads or writes the data.
    • NI 6584 Static Generation and Acquisition - NoTerm (Full Duplex).lvproj—This example demonstrates how to generate and acquire a static pattern from the NI 6584. Static generation places a single pattern on the configured lines. Static acquisition samples the configured channels once, returning data as a Boolean array. Both static generation and acquisition are controlled by software and do not use status signals or hardware timing. The FPGA continuously generates and acquires data, but the host VI determines the rate at which the device reads or writes the data.
  • Half Duplex
    • NI 6584 Basic Software UART Half Duplex - NoTerm.lvproj—This example implements the basic functionality of a UART (universal asynchonous receiever/transmitter). It can generate and receive data from basic UART (no flow control). The default channel for this UART to run is Channel 0.
    • NI 6584 Basic Software UART Half Duplex.lvproj—This example implements the basic functionality of a UART (universal asynchonous receiever/transmitter). It can generate and receive data from basic UART (no flow control). The default channel for this UART to run is Channel 0.
    • NI 6584 Finite Acquisition with External Clk - NoTerm (Half Duplex).lvproj—This example acquires a finite number of samples using an external clock and passes the data to the host VI through an Acquisition FIFO.
    • NI 6584 Finite Acquisition with External Clock (Half Duplex).lvproj—This example acquires a finite number of samples using an external clock and passes the data to the host VI through an Acquisition FIFO.
    • NI 6584 Finite Acquisition and Exported Clock (Half Duplex).lvproj—This example acquires a finite number of samples using an external clock and passes the data to the host VI through an Acquisition FIFO.
    • NI 6584 Finite Generation Exported Clk - NoTerm (Half Duplex).lvproj—This example generates a finite number of parallel samples and exports the onboard clock to the Clock BNC connnector on the NI 6584. The example also outputs a data active signal on the PFI BNC connector while data is being generated. It uses a Generation FIFO to pass an array of samples from the host to the target to be generated.
    • NI 6584 Static Generation and Acquisition (Half Duplex).lvproj—This example demonstrates how to generate and acquire a static pattern from the NI 6584. Static generation places a single pattern on the configured lines. Static acquisition samples the configured channels once, returning data as a Boolean array. Both static generation and acquisition are controlled by software and do not use status signals or hardware timing. The FPGA continuously generates and acquires data, but the host VI determines the rate at which the device reads or writes the data.
    • NI 6584 Static Generation and Acquisition - NoTerm (Half Duplex).lvproj—This example demonstrates how to generate and acquire a static pattern from the NI 6584. Static generation places a single pattern on the configured lines. Static acquisition samples the configured channels once, returning data as a Boolean array. Both static generation and acquisition are controlled by software and do not use status signals or hardware timing. The FPGA continuously generates and acquires data, but the host VI determines the rate at which the device reads or writes the data.

For more information about using an example project to get started with the NI 6584, refer to the NI 6584R User Guide and Specifications document, shipped with your device and available at ni.com/manuals.

CLIP I/O Signals

The following table describes the NI 6584 Channel CLIP I/O signals.

CLIP Signal Name Data Type NI 6584 VHDCI Connector Pin (Full Duplex) NI 6584 VHDCI Connector Pin (Half Duplex) NI 6584 Connector Signal Description
RX_0 Bool 64, 66 61, 67 RX_0+, RX_0–,

(GLOBAL CLK 0+,

GLOBAL CLK 0–)
RS-485/422 channel input
RX_1 Bool 68, 63 65, 62 RX_1+, RX_1–
RX_2 Bool 55, 57 52, 58 RX_2+, RX_2–
RX_3 Bool 59, 54 56, 53 RX_3+, RX_3–
RX_4 Bool 47, 49 44, 50 RX_4+, RX_4–
RX_5 Bool 51, 46 48, 45 RX_5+, RX_5–
RX_6 Bool 38, 40 35, 41 RX_6+, RX_6–
RX_7 Bool 42, 37 39, 36 RX_7+, RX_7–
RX_8 Bool 30, 32 27, 33 RX_8+, RX_8–
RX_9 Bool 34, 29 31, 28 RX_9+, RX_9–
RX_10 Bool 21, 23 18, 24 RX_10+, RX_10–
RX_11 Bool 25, 20 22, 19 RX_11+, RX_11–
RX_12 Bool 13, 15 10, 16 RX_12+, RX_12–
RX_13 Bool 17, 12 14, 11 RX_13+, RX_13–
RX_14 Bool 4, 6 1, 7 RX_14+, RX_14–
RX_15 Bool 8, 3 5, 2 RX_15+, RX_15–
TX_0 Bool 61, 67 61, 67 TX_0+, TX_0– RS-485/422 channel output
TX_1 Bool 65, 62 65, 62 TX_1+, TX_1–
TX_2 Bool 52, 58 52, 58 TX_2+, TX_2–
TX_3 Bool 56, 53 56, 53 TX_3+, TX_3–
TX_4 Bool 44, 50 44, 50 TX_4+, TX_4–
TX_5 Bool 48, 45 48, 45 TX_5+, TX_5–
TX_6 Bool 35, 41 35, 41 TX_6+, TX_6–
TX_7 Bool 39, 36 39, 36 TX_7+, TX_7–
TX_8 Bool 27, 33 27, 33 TX_8+, TX_8–
TX_9 Bool 31, 28 31, 28 TX_9+, TX_9–
TX_10 Bool 18, 24 18, 24 TX_10+, TX_10–
TX_11 Bool 22, 19 22, 19 TX_11+, TX_11–
TX_12 Bool 10, 16 10, 16 TX_12+, TX_12–
TX_13 Bool 14, 11 14, 11 TX_13+, TX_13–
TX_14 Bool 1, 7 1, 7 TX_14+, TX_14–
TX_15 Bool 5, 2 5, 2 TX_15+, TX_15–
TX_Enable_0 Bool TX_0_Enable RS-485/422 channel output enable
TX_Enable_1 Bool TX_1_Enable
TX_Enable_2 Bool TX_2_Enable
TX_Enable_3 Bool TX_3_Enable
TX_Enable_4 Bool TX_4_Enable
TX_Enable_5 Bool TX_5_Enable
TX_Enable_6 Bool TX_6_Enable
TX_Enable_7 Bool TX_7_Enable
TX_Enable_8 Bool TX_8_Enable
TX_Enable_9 Bool TX_9_Enable
TX_Enable_10 Bool TX_10_Enable
TX_Enable_11 Bool TX_11_Enable
TX_Enable_12 Bool TX_12_Enable
TX_Enable_13 Bool TX_13_Enable
TX_Enable_14 Bool TX_14_Enable
TX_Enable_15 Bool TX_015_Enable
Clock_Out Bool BNC clock out
Clock_Out_Enable Bool BNC clock out enable
Clock_Out_Invert Bool Inverts BNC clock out
PFI_Input Bool BNC PFI input
PFI_Output Bool BNC PFI output
PFI_Output_Enable Bool BNC PFI output enable
BNC Clock Bool 64, 66 61, 67 BNC Clock In (GLOBAL CLK 0+,

GLOBAL CLK 0–)
External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties Dialog and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
RX_0 Clock Bool RX_0+, RX_0–,

(GLOBAL CLK 1+,

GLOBAL CLK 1–)
External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
Clock Out Bool   Use this signal to export any available clock source through BNC Clock Out.

NI 6584 Channel CLIP Clocks

The following table describes the NI 6584 Channel CLIP clock signals.

CLIP Signal Name Description
BNC Clock* External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties Dialog and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
RX_0 Clock* External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
Clock Out* Use this signal to export any available clock source through BNC Clock Out.
*BNC CLock Out, RX_0 Clock, and Clock Out are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
14.1 and later FlexRIO Adapter Module Support 14.1 and later BNC Clock, RX_0 Clock, and Clock Out
1.2 and earlier FlexRIO Adapter Module Support 14.0 and earlier IO Module Clock 0 and IO Module Clock 1

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