NI 6584 Basic Connector CLIP Reference

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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This CLIP provides read/write access to all RS-485/422 lines. This CLIP has 16 data output lines, 16 data input lines, 16 data output enable lines, one clock I/O, one clock output enable, one PFI I/O, and one PFI output enable. This CLIP also allows for clock output inversion. The input lines are always enabled. In the LabVIEW FPGA Module, the data inputs, data outputs, and data enables are accessed using a U16 data type. The Clock_Out, Clock_Out_Enable, Clock_Out_Invert, and PFI lines are all accessed using a Boolean signal.

This CLIP allows you to import or export a clock using the Clock BNC connector. When exporting an FPGA-generated clock, it can be inverted before it is generated. Inverting this clock allows you to synchronize the output data to either the rising or falling edge of the clock. Setting the Clock_Out_Invert signal to FALSE synchronizes the data with the rising edge, and setting the Clock_Out_Invert signal to TRUE synchronizes the data with the falling edge. A clock can also be imported on RX_0 if that channel is not used as a data line. To use RX_0 as a clock, add IOModuleCLIPClock0 to your LabVIEW FPGA project.

FlexRIO support installation includes a variety of example projects to help get you started with the NI 6584 Basic Connector CLIP. To access these examples in NI Example Finder, open LabVIEW and select Help»Find Examples, then select Hardware Input and Output»FlexRIO»IO Modules»NI 6584.

Note  This folder contains examples for full duplex, full duplex no termination, half duplex, and half duplex no termination devices. Depending on your version of the NI 6584, select the appropriate examples for your device.

The following example projects use the I/O signals exposed by the NI 6584 Basic Connector CLIP:

  • NI 6584 Finite Acquisition with External Clock (Full Duplex).lvproj
  • NI 6584 Finite Acquisition with External Clock - NoTerm (Full Duplex).lvproj
  • NI 6584 Finite Acquisition with External Clock (Half Duplex).lvproj
  • NI 6584 Finite Acquisition with External Clock - NoTerm (Half Duplex).lvproj
  • NI 6584 Finite Generation and Exported Clock (Full Duplex).lvproj
  • NI 6584 Finite Generation and Exported Clock - NoTerm (Full Duplex).lvproj
  • NI 6584 Finite Generation and Exported Clock (Half Duplex).lvproj
  • NI 6584 Finite Generation and Exported Clock - NoTerm (Half Duplex).lvproj

For more information about using an example project to get started with the NI 6584, refer to the NI 6584R User Guide and Specifications document, shipped with your device and available at ni.com/manuals.

The following table describes the NI 6584 Connector CLIP I/O signals.

CLIP Signal Name Data Type Bit NI 6584 VHDCI Connector Pin (Full Duplex) NI 6584 VHDCI Connector Pin (Half Duplex) NI 6584 Connector Signal Description
RX U16 0 64, 66 61, 67 RX_0+, RX_0– RS-485/422 channel input
1 68, 63 65, 62 RX_1+, RX_1–
2 55, 57 52, 58 RX_2+, RX_2–
3 59, 54 56, 53 RX_3+, RX_3–
4 47, 49 44, 50 RX_4+, RX_4–
5 51, 46 48, 45 RX_5+, RX_5–
6 38, 40 35, 41 RX_6+, RX_6–
7 42, 37 39, 36 RX_7+, RX_7–
8 30, 32 27, 33 RX_8+, RX_8–
9 34, 29 31, 28 RX_9+, RX_9–
10 21, 23 18, 24 RX_10+, RX_10–
11 25, 20 22, 19 RX_11+, RX_11–
12 13, 15 10, 16 RX_12+, RX_12–
13 17, 12 14, 11 RX_13+, RX_13–
14 4, 6 1, 7 RX_14+, RX_14–
15 8, 3 5, 2 RX_15+, RX_15–
TX U16 0 61, 67 61, 67 TX_0+, TX_0– RS-485/422 channel output
1 65, 62 65, 62 TX_1+, TX_1–
2 52, 58 52, 58 TX_2+, TX_2–
3 56, 53 56, 53 TX_3+, TX_3–
4 44, 50 44, 50 TX_4+, TX_4–
5 48, 45 48, 45 TX_5+, TX_5–
6 35, 41 35, 41 TX_6+, TX_6–
7 39, 36 39, 36 TX_7+, TX_7–
8 27, 33 27, 33 TX_8+, TX_8–
9 31, 28 31, 28 TX_9+, TX_9–
10 18, 24 18, 24 TX_10+, TX_10–
11 22, 19 22, 19 TX_11+, TX_11–
12 10, 16 10, 16 TX_12+, TX_12–
13 14, 11 14, 11 TX_13+, TX_13–
14 1, 7 1, 7 TX_14+, TX_14–
15 5, 2 5, 2 TX_15+, TX_15–
TX_Enable U16 0 TX_0_Enable RS-485/422 channel output enable
1 TX_1_Enable
2 TX_2_Enable
3 TX_3_Enable
4 TX_4_Enable
5 TX_5_Enable
6 TX_6_Enable
7 TX_7_Enable
8 TX_8_Enable
9 TX_9_Enable
10 TX_10_Enable
11 TX_11_Enable
12 TX_12_Enable
13 TX_13_Enable
14 TX_14_Enable
15 TX_15_Enable
Clock_Out Bool BNC clock out
Clock_Out_Enable Bool BNC clock out enable
Clock_Out_Invert Bool Inverts BNC clock out
PFI_Input Bool BNC PFI input
PFI_Output Bool BNC PFI output
PFI_Output_Enable Bool BNC PFI output enable
BNC Clock Bool 64, 66 61, 67 BNC Clock In (GLOBAL CLK 0+,

GLOBAL CLK 0–)
External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties Dialog and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
RX_0 Clock Bool RX_0+, RX_0–,

(GLOBAL CLK 1+,

GLOBAL CLK 1–)
External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
Clock Out Bool   Use this signal to export any available clock source through BNC Clock Out.

NI 6584 Channel CLIP Clocks

The following table describes the NI 6584 Channel CLIP clock signals.

CLIP Signal Name Description
BNC Clock* External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties Dialog and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
RX_0 Clock* External Sample clock source that can be used for dynamic acquisition. This clock is accessed in the FPGA Base Clock Properties dialog box and is added to your LabVIEW project in Clock Selections category of the IO Module Properties dialog box.
Clock Out* Use this signal to export any available clock source through BNC Clock Out.
*BNC CLock Out, RX_0 Clock, and Clock Out are only available with certain versions of the CLIP and LabVIEW FPGA. Refer to the table below to determine which clock signal you must use.

FPGA Clock Requirements


Version of CLIP Version of FlexRIO Adapter Module Support Available FPGA Clock
14.1 and later FlexRIO Adapter Module Support 14.1 and later BNC Clock, RX_0 Clock, and Clock Out
1.2 and earlier FlexRIO Adapter Module Support 14.0 and earlier IO Module Clock 0 and IO Module Clock 1

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