Owning Palette: Structures
Requires: FPGA Module. This topic might not match its corresponding palette in LabVIEW depending on your operating system, licensed product(s), and target.
Use the Timed Loop structure to control the rate at which a subdiagram executes.
|FPGA Clock Constant||Use the FPGA clock constant to specify an FPGA clock on the block diagram.|
|Start Disabling FPGA Clock||Starts disabling an FPGA clock to protect circuitry dependent on a periodic clock. Use this VI to disable the clock prior to glitches or before the clock signal becomes unavailable. Clocks that support and require enabling and disabling at run time begin disabled after you download or reset the FPGA VI. When you reenable the clock using the Start Enabling FPGA Clock VI, the state of all registers and memory using the disabled clock is the same as the last cycle before the clock was disabled.|
|Start Enabling FPGA Clock||Starts enabling an FPGA clock. To ensure data integrity, the clock you want to enable must be glitch free and free running. When you reenable the clock using this VI, the state of all registers and memory using the disabled clock is the same as the last cycle before the clock was disabled.|
|Timed Loop||The FPGA Module single-cycle Timed Loop differs from the standard LabVIEW Timed Loop in that the timing of the FPGA single-cycle Timed Loop corresponds exactly to the clock rate of the FPGA clock you specify. By configuring a single-cycle Timed Loop to use a clock other than the base clock of the FPGA target, you can implement multiple clock domains in an FPGA VI. You can specify the FPGA clock that controls the single-cycle Timed Loop by wiring a value to the Source Name input on the Input Node of the single-cycle Timed Loop or by using the Configure Timed Loop dialog box.|