Requires: FPGA Module
Reads from memory available on the FPGA target. If the memory is configured for both read and write access, you can use this method in conjunction with the Write method. If you configure the memory for dual port read access, the label includes an [A] or [B] to indicate which interface this node will access.
Use the Memory Method Node to implement this method.
|Block Diagram Inputs|
|Block Diagram Outputs|
|Memory In||Specifies the FPGA memory. You can wire a Memory control, Memory constant, VI-Defined Memory Configuration node, or another Memory Method Node to Memory In.|
|Address||Specifies the location of the data in memory on the FPGA target. The valid address range depends on the Requested number of elements you specify on the General page of the Memory Properties dialog box. For example, if you specify a Requested number of elements of 1000, the valid address range is 0–999. If Address exceeds the address range, the Read method returns an error and the output data might be invalid. Add error terminals so LabVIEW can notify you if Address exceeds the address range.|
|Memory Out||Returns Memory In if Memory In is wired. Otherwise, Memory Out returns the memory that you specify in the Memory Method Node.|
|Data||Returns the data read from memory on the FPGA target. Data is directly accessible only from within the FPGA VI. You cannot directly access the data in the memory of the FPGA target from the host VI. You must use controls, indicators, or DMA FIFOs to access data from the host VI. The Data data type is the data type you configure in the Memory Properties dialog box when you create the memory item. If you do not initialize the memory item, the data is undefined.|
Consider the following when you use this node inside a single-cycle Timed Loop:
|Note Selecting the Never Arbitrate option when simulating an FPGA application that contains memory items with multiple accessors may result in incorrect behavior. For example, if your application includes multiple writers, each writer can update the memory address specified during simulation. Additionally, if your application includes multiple readers, each reader can assess the memory address specified during simulation.|
If you implement the memory item using block memory, the number of cycles required for the Read (Memory Method) to produce a valid Data value is equal to the number of cycles of read latency. The number under the icon at the top of the Read (Memory Method) node indicates the number of cycles of latency.
Inside the single-cycle Timed Loop, the number of Feedback Nodes or uninitialized shift registers wired to the Data output of the Read (Memory Method) node must be greater than or equal to the number of cycles of read latency. If you use Feedback Nodes, each Feedback Node must not display the enable terminal. If any Feedback Node displays the enable terminal or you do not wire enough Feedback Nodes or uninitialized shift registers after the Read (Memory Method), the FPGA VI fails to compile and LabVIEW returns an error.
|Note LabVIEW supports initialization of Feedback Nodes following the Read (Memory Method) only when Cycles of read latency is set to 1.|
If you implement the memory item using look-up tables, you do not need to wire the node output directly to a Feedback Node or uninitialized shift register. You can read from the memory item during the same cycle in which you provide the Address.
|Caution When you use memory items implemented using block memory in multiple clock domains, it is possible to read from and write to the same address simultaneously. Doing so can result in reading incorrect data.|