Write (Memory Method)

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Requires: FPGA Module

Writes to memory available on the FPGA target.

Use the Memory Method Node to implement this method.

Details  

Block Diagram Inputs
Block Diagram Outputs

Block Diagram Inputs

ParameterDescription
Memory InSpecifies the FPGA memory. You can wire a Memory control, Memory constant, VI-Defined Memory Configuration node, or another Memory Method Node to Memory In.
AddressSpecifies the location of the data in memory on the FPGA target. The valid address range depends on the Requested number of elements you specify in the Memory Properties dialog box. For example, if you specify a Requested number of elements of 65536, the valid address range is 0–65535. If Address exceeds the address range, the Memory Method Node returns an error and does not write the data. Add error terminals so LabVIEW can notify you if Address exceeds the address range.
DataIs the data to write to the memory on the FPGA target. You can directly write to Data only from the FPGA VI. You cannot directly write to the data in the memory of the FPGA target from the host VI. You must use controls, indicators, or DMA FIFOs to access data from the host VI. If you do not initialize the memory item, the data is undefined.
Byte EnablesSpecifies which bytes of data are enabled when this node writes data to memory. The least significant bit corresponds to the least significant byte of data, the second least significant bit corresponds to the second least significant byte of data, and so on. By default, Byte Enables is an integer of all ones, large enough to enable all bytes for the target. To display this terminal, configure the memory as DRAM, then right-click the node and select Show Byte Enables from the pull-down menu. Refer to your target hardware documentation for more information about the DRAM width in bytes for your target.
Input ValidSpecifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node.

To display this handshaking terminal, configure the memory as DRAM.

Block Diagram Outputs

ParameterDescription
Memory OutReturns Memory In if Memory In is wired. Otherwise, Memory Out returns the memory that you specify in the Memory Method Node.
Ready for InputReturns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.
To display this terminal, configure the memory as DRAM.

Write (Memory Method) Details

Use this method in conjunction with the Read method when you implement the memory using block memory or LUTs. Use this method in conjunction with the Request Data and Retrieve Data methods when you implement the memory using DRAM.

Note  The corresponding Request Data and Retrieve Data method nodes can be placed in a different clock domain.

Considerations for Single-Cycle Timed Loops

  • If you use this node in a single-cycle Timed Loop, you must set the Write option on the Interfaces page to Arbitrate if Multiple Requestors Only or Never Arbitrate, and you cannot use this node with the same memory item anywhere else in the FPGA VI.
    Note  Selecting the Never Arbitrate option when simulating an FPGA application that contains memory items with multiple accessors may result in incorrect behavior. For example, if your application includes multiple writers, each writer can update the memory address specified during simulation. Additionally, if your application includes multiple readers, each reader can assess the memory address specified during simulation.
  • The Memory Method Node takes an entire clock cycle to execute.
  • You can use a target-scoped or VI-defined memory item to store data and access it from a different clock domain only if you implement the memory item using block memory. In this implementation, you can use only one writer node and one reader node for each memory item.
    Caution  When you use memory items implemented using block memory in multiple clock domains, it is possible to read from and write to the same address simultaneously. Doing so can result in reading incorrect data.
  • If the memory is DRAM, you must use this method in a single-cycle Timed Loop.

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