Some FPGA targets contain onboard dynamic random access memory (DRAM) that you can access directly from the FPGA VI. LabVIEW supports two types of DRAM interface:
Most FPGA applications using DRAM can take advantage of the usability and VHDL optimization that the FPGA memory item interface provides. However, you can still use the socketed CLIP interface for access to raw addresses using I/O signals. You cannot use both FPGA memory items and socketed CLIP to access the same DRAM bank in a VI. You cannot use VI-defined memory items to configure DRAM.
Complete the following steps to determine whether DRAM is available for your target.
|Note If DRAM is not available for your target, the Memory Properties dialog box does not list DRAM as an option under the Implementation pull-down menu.|
You can use the FPGA memory item interface to partition the physical DRAM banks available on a target into multiple memory items. Use the Memory Properties dialog box to create and configure memory partitions on a DRAM bank. For example, if a target has two physical DRAM banks, you could partition one bank into three different memories and the other bank into five memories, as shown below. LabVIEW treats each memory independently of each other.
After you create the memory partitions, you must configure the arbitration between partitions in the same DRAM bank using the DRAM Properties page of the FPGA Target Properties dialog box.
If you partition the DRAM into multiple memory items, you can configure the amount of time LabVIEW grants to each partition. By default, LabVIEW grants equal time to all partitions. This DRAM arbiter is not the same arbiter that arbitrates between different requestors of the same shared resource.
Access to DRAM involves some non-deterministic latency. To compensate for this latency, use the Request Data and Retrieve Data methods to read data from DRAM. You can queue multiple requests for data using the Request Data method and retrieve requested data using the Retrieve Data method. The DRAM returns requested data when you indicate you are ready to receive it using handshaking signals.
To optimize DRAM performance, send requests for data or write data to the DRAM in bursts, such as on each clock cycle.