Interfaces Page (Memory Properties Dialog Box)

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

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Requires: FPGA Module

In the Memory Properties dialog box, select Interfaces from the Category list to display this page.

Use this page to configure the arbitration options and to specify read and/or write ports for the memory item.

This page includes the following components:

  • Dual Clock Interface—Specifies that you can write data to the memory item in one clock domain and read from the memory item in a different clock domain. This option is available only for memory items implemented using block memory. The default is unchecked.
    Caution  When you use memory items implemented using block memory in multiple clock domains, it is possible to read and write from the same address simultaneously. Doing so can result in reading incorrect data.
  • Interface A—Specifies the type of arbitration for reading from Interface A.
  • Interface B—Specifies the method and type of arbitration for Interface B.
  • Memory Schematic Diagram—Reflects the configuration of the memory block.


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