General Page (Memory Properties Dialog Box)

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

»View Product Info

»Download the Help in ZIP Format

Requires: FPGA Module

In the Memory Properties dialog box, select General from the Category list to display this page.

Use this page to edit properties for memory items.

This page includes the following components:

  • Name—Specifies the name of the memory item that appears in the Project Explorer window or in the VI-Defined Memory Configuration node. The name also appears in the Memory Method Node on the block diagram.
  • Requested number of elements—Specifies the number of elements you want to hold in the memory item. The actual memory usage, in bytes, depends on the number of elements and the data type you specify.
  • Implementation—Specifies how the FPGA stores this memory item. Contains the following options:
    • Block Memory—Stores the data using embedded blocks of memory. Xilinx describes this implementation as block RAM or BRAM. Memory items using embedded block memory take at least one clock cycle to execute. Use block memory in the following situations:

      • In a single-cycle Timed Loop, when you do not need to access this memory during the same cycle as the one in which you provide the address.

      • When the amount of memory you need is large.

      • When you do not have enough free resources available on the FPGA.

      This option contains the following components:
      • Actual number of elements—Returns the configured number of elements. Sometimes the requested number of elements is not compatible with the memory configuration. In this case, LabVIEW coerces the Actual number of elements to a compatible number.
      • Cycles of read latency—Specifies the number of cycles of latency for the Read (Memory Method) of memory items implemented using block memory. The default value is 2 cycles of latency. An increase in cycles of read latency results in an increase in internal pipelining, which also can increase the maximum frequency of your compiled design. The number of cycles required for the Read (Memory Method) to produce valid data is equal to the number of Cycles of read latency.
        Note  When you use the Read (Memory Method) within the single-cycle Timed Loop for a memory item implemented using block memory, the number of Feedback Nodes or uninitialized shift registers wired to the data output must be greater than or equal to the number of Cycles of read latency. If you do not wire enough Feedback Nodes or uninitialized shift registers after the Read (Memory Method), the FPGA VI fails to compile and LabVIEW returns an error.
    • Look-Up Table—Stores the memory item in look-up tables available on the FPGA. This storage consumes FPGA resources that the FPGA uses for other logical operations, such as addition and subtraction. Xilinx describes this implementation as distributed RAM or LUT RAM. Use look-up tables in the following situations:

      • You are accessing this memory in a single-cycle Timed Loop and need to read data from the memory item during the same cycle as the one in which you provide the address.

      • The amount of memory you need is smaller than the minimum amount of embedded block memory on the FPGA.

      • You do not have enough free embedded block memory on the FPGA.

      This option contains the following component:
      • Actual number of elements—Returns the configured number of elements. Sometimes the requested number of elements is not compatible with the memory configuration. In this case, LabVIEW coerces the Actual number of elements to a compatible number.
    • DRAM—Stores the memory item in DRAM available on the FPGA. Not all hardware supports using DRAM for memory. See the DRAM Properties page of the FPGA Target Properties dialog box to configure how LabVIEW implements DRAM in the project. This option contains the following components:
      • Actual number of elements—Returns the configured number of elements. Sometimes the requested number of elements is not compatible with the memory configuration. In this case, LabVIEW coerces the Actual number of elements to a compatible number.
      • Maximum outstanding requests for data—Specifies the number of maximum requests for data that the application allows to be outstanding.
      • DRAM bank—Specifies which DRAM bank to use.
        • Allocated here—Indicates the amount of memory allocated in this memory item.
        • Allocated elsewhere—Indicates how much memory is allocated in other items.
        • Available—Indicates how much memory is still available in the bank.
        • Total physical size—Indicates the total size of the bank.
  • Persist memory values between VI executions while executing on the development computer—If you do not place a checkmark in this checkbox, the values in this memory item reset to the initial values as specified on the Initial Values page of the Memory Properties dialog box between VI executions while executing on the development computer. If you place a checkmark in this checkbox, LabVIEW retains values in this memory item between VI executions while executing on the development computer but may result in higher memory consumption and slower execution for large memories. By default, this checkbox does not contain a checkmark for new LabVIEW projects.
    Note  The checkbox contains a checkmark for previous versions of LabVIEW projects in order to maintain the behavior of previous versions of FPGA applications.

WAS THIS ARTICLE HELPFUL?

Not Helpful