Code Generation Error Codes (FPGA Module)

FlexRIO Help

Edition Date: November 2015

Part Number: 372614J-01

»View Product Info

»Download the Help in ZIP Format

The FPGA Module can return the following code generation error codes. Refer to the KnowledgeBase for more information about correcting errors in LabVIEW.

Code Description
−61507 Peer-to-peer FIFOs are unsupported on the current target. Specify another type for your FIFO, or you can specify another target if you want to use peer-to-peer FIFOs.
−61505 Unsupported .xci file. Component-level IP (CLIP) does not support the <FileName> file, because this file is created by an old version of Xilinx Vivado. Specify another .xci file that is created by Xilinx Vivado <ToolVersion>.
−61503 Missing required Xilinx compilation tools. Install the Xilinx <ToolVersion> compilation tools from the appropriate DVD.
−61502 File format mismatch. Component-Level IP (CLIP) does not support certain synthesis files under current targets and the compilation will not include these files. xci, dcp, and xdc file types are supported only by Xilinx Vivado targets. ucf, xco, ngd, vhe, pxml, ngm, and ngd files are supported only by Xilinx ISE targets.
−61489 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: The block diagram or project contains an item that FPGA DFIR cannot handle.
−61474 "FFT size" must be greater than or equal to the number of samples per input.
−61473 The "imaginary data" input array size is different from that of the "real data" input. The array sizes of these inputs must be the same.
−61472 The input array size must be 2, 4, 8, or 16.
−61471 You must reload the IO Module declaration file. The IO Module declaration file has been updated on disk since its last association with this LabVIEW project. On the General page of the IO Module Properties dialog box, click Reload.
−61470 You must reload the DRAM declaration file. The Memory Interface DRAM declaration file has been updated on disk since its last association with this LabVIEW project. On the General page of the DRAM Properties dialog box, click Reload.
−61414 Control or indicator data type is not supported. The data type of the control or indicator is not supported on the FPGA. Note that controls and indicators are not removed from the VI during compilation, even if their block diagram terminals are placed inside of a Diagram Disable Structure.
−61355 An internal software error has occurred. DFIR refnum not found.
−61354 Internal software error(s): Connected node is not constant. A terminal is not connected to a constant.
−61353 Internal software error(s): Output terminal not supported. The current operation is allowed only on input terminals, and the terminal on this block diagram object is an output terminal.
−61352 Internal software error(s): Terminal is not connectable. You are trying to access a connector pane terminal that is not configured as an input or output.
−61351 Internal software error(s): Terminal is unconnected. A block diagram object terminal is unconnected.
−61350 Internal software error(s): Terminal Index Out of Bounds. A terminal with this index does not exist on this block diagram node.
−61345 Unresolved LabVIEW class. LabVIEW cannot determine the static class type of the global variable because the class written to it does not match the type of the global variable's default value. Ensure that all writes to the global variable use the same class type as its default value.
−61344 The array contains arrays of varying sizes. The FPGA Module does not support global variables with default values that contain embedded arrays of varying sizes.
−61343 Unresolved LabVIEW class. The LabVIEW class could not be statically resolved because different classes are wired to separate calls to the non-reentrant VI. Ensure that all calls to the VI use the same classes. Call chain: <CallChain>
−61341 The array contains arrays of varying sizes. The LabVIEW FPGA Module does not support insertion of array elements that result in embedded arrays of varying sizes. Call chain: <CallChain>
−61339 The top-level VI contains a variable-sized array control or indicator. The FPGA Module does not support variable-sized arrays on the front panel of the top-level VI.
−61338 Array does not resolve to a fixed size. LabVIEW cannot determine the size of the array on the local or global variable because arrays of different sizes are written to it. Ensure that all writes to the local or global variable use arrays of the same size.
−61337 Array does not resolve to a fixed size. LabVIEW cannot determine the size of the array on the control or indicator because arrays of different sizes are wired to separate calls to the non-reentrant VI. Ensure that all calls to the VI use array inputs of the same size.
−61336 The While Loop contains an auto-indexed output tunnel. The FPGA Module does not support auto-indexed output tunnels on the While Loop.
−61335 Array does not resolve to a fixed size. LabVIEW cannot determine the size of the array output tunnel because the For Loop does not execute a fixed number of times. This may occur if the N-input is wired to a non-constant value or if the loop contains auto-indexed input tunnels that are wired to variable-sized arrays. Call chain: <CallChain>
−61334 Array does not resolve to a fixed size. LabVIEW cannot determine the size of the array output because a node input is a non-constant value. Ensure that all index and length inputs resolve to constant values. Call chain: <CallChain>
−61333 Array does not resolve to a fixed size. LabVIEW cannot determine the size of the array output because arrays of different sizes are wired to the node. Ensure that all array inputs resolve to the same size. Call chain: <CallChain>
−61323 The current target has no available DCMs for the CLIP. You have included the CLIP <CLIPInstantiationName> that uses <NumberOfUsedDCMs> Digital Clock Managements (DCMs), but the current target does not have any available DCMs. Remove or alter the CLIP, or use the CLIP on a target with available DCMs.
−61322 The current target has no available MMCMs for the CLIP. You have included the CLIP <CLIPInstantiationName> that uses <NumberOfUsedMMCMs> Mixed-Mode Clock Managers (MMCMs), but this target does not have any available MMCMs. Remove or alter the CLIP, or use the CLIP on a target with available MMCMs.
−61310 A clock is not supported on this target. Clock <DerivedExternalClock> is derived from an external clock or a CLIP clock. Virtex 2 and Spartan 3 targets do not support derived clocks from external or CLIP clocks.
−61309 A node requires a synchronous reset but the build spec allows enable removal. One or more nodes requires a synchronous reset signal. When the application is configured to allow the removal of implicit enable signals, LabVIEW does not support placing a node with this requirement inside a single-cycle Timed Loop controlled either by an external clock or by a clock that supports gating. Remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification or change to a timing source that does not support gating.
−61308 A node is not supported when the application allows enable removal. One or more nodes do not specify the required number of cycles during asynchronous reset. When the application is configured to allow the removal of implicit enable signals, LabVIEW does not support placing a node with this requirement inside a single-cycle Timed Loop controlled either by an external clock or by a clock that supports gating. Remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification or configure the required number of cycles for the node.
−61307 A node requiring a running clock during reset is in an application allowing enable removal. The node requires a running clock during asynchronous reset. When the application is configured to allow the removal of implicit enable signals, you cannot place a node with this requirement inside a single-cycle Timed Loop that is controlled either by an external clock or by a clock that supports gating. Reconfigure or remove the node, or remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification.
−61306 This CLIP is not supported for applications that allow enable removal. The CLIP, <ClipName>, does not specify the required number of cycles during asynchronous reset for one or more of its clock inputs and is connected either to an external clock or to a clock that supports gating. You cannot use a CLIP with this requirement inside an application configured to allow the removal of implicit enable signals. Reconfigure or remove the CLIP, or remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification.
−61305 This CLIP is not supported for applications that allow enable removal. The CLIP, <ClipName>, requires a running clock during asynchronous reset and is connected either to an external clock or to a clock that supports gating. You cannot use a CLIP with this requirement in an application configured to allow the removal of implicit enable signals. Reconfigure or remove the CLIP, or remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification.
−61299 A loop requires enable removal but the build spec does not support it. You must enable the required option in the build specification in order to allow the removal of implicit enable signals for this loop. Remove the checkmark from the "Require removal of implicit enable signals" checkbox in the Configure Timed Loop dialog box or place a checkmark in the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification. Note that allowing the removal of implicit enable signals will restrict the host interface methods that you can use with this bitfile. Refer to the LabVIEW Help for more information about allowing the removal of implicit enable signals. The build specification option is only available on targets that support it.
−61298 This target does not support enable removal. The build specification is configured to allow the removal of implicit enable signals but the target does not support enable removal. Remove the checkmark from the "Allow removal of implicit enable signals in single-cycle Timed Loops" checkbox in the build specification.
−61297 A loop controlled by a clock that does not support gating requires enable removal. LabVIEW does not support the removal of implicit enable signals from loops controlled by clocks that do not support gating. Replace the clock source with one that supports gating or remove the checkmark from the "Require removal of implicit enable signals" checkbox in the Configure Timed Loop dialog box.
−61296 A loop that requires enable removal conditionally stops executing. LabVIEW does not support the removal of implicit enable signals from loops that conditionally stop executing. Valid stop conditions for this loop are unwired Stop if True, Stop if True wired to a FALSE constant, or Continue if True wired to a TRUE constant. Reconfigure the stop condition for the loop or remove the checkmark from the "Require removal of implicit enable signals" checkbox in the Configure Timed Loop dialog box.
−61295 A loop that requires enable removal has dataflow dependencies. LabVIEW requires the enable chain signals to enforce dataflow execution between code inside and outside the loop. Remove the checkmark from the "Require removal of implicit enable signals" checkbox in the Configure Timed Loop dialog box or ensure that code inside the loop does not depend on data computed outside the loop.
−61294 The size of the selected data type is too large for the selected DRAM. The size of the data type for <MemoryName> is too large for <DramBankName>. The size of the data type, which is <Size> bits, must be less than or equal to the DRAM port width, which is <DramPortWidth> bits.
−61293 Insufficient DRAM available for allocation of memories. <DramBankName> is not large enough to allocate the requested memory items. The following memory items have been requested: <MemoryList> Reduce the total amount of memory requested to <DramBankSize> MB.
−61292 Missing Method(s) for DRAM-based memory. The following method(s) are missing for <MemoryName>: <MissingMethodList>. All DRAM-based memory items require Write, Request Data and Retrieve Data methods.
−61291 Request Data and Retrieve Data memory methods must be in the same clock domain. Request Data and Retrieve Data methods for <MemoryName> must be placed in the same clock domain.
−61290 DRAM Memory Method Not Supported Outside SCTL. <MethodName> for <MemoryName> is not supported outside single-cycle Timed Loops (SCTLs). Methods available for DRAM-based memory items are supported only inside SCTLs.
−61250 Corrupt or missing Xilinx installation. Exporting FPGA VIs for simulation requires Xilinx version 11.5 or greater. The Xilinx compilation tools are either not installed or corrupt. Install or repair the Xilinx compilation tools to export FPGA Vis for simulation.
−61247 The VI cannot be compiled for FPGA. The VI belongs to an NI toolkit that is currently in evaluation mode.
−61246 Missing resource definition for FIFO, Memory, or Register method. The node refers to an undefined hardware resource. This can occur if the local FIFO, memory, or register resource is placed in a diagram disable structure. Move the resource definition out of the disable structure or delete the method node.
−61245 The VI cannot be compiled for FPGA. The VI belongs to a toolkit that is currently in evaluation mode. To purchase this product, please contact the vendor of the toolkit. If you have already purchased this product, select Help >> Activate Add-ons to activate this product.
−61244 The VI cannot compile without a block diagram. The LabVIEW FPGA Module does not support VIs saved without block diagrams.
−61243 The array does not meet implementation requirements. The array could not be implemented using the resource type specified. This occurs when either Block Memory or Look-Up Tables is selected and the usage of the array does not meet the limitations of the resource. Restructure the array in order to obtain the desired implementation or change the FPGA Implementation option to Auto.
−61242 The FPGA Module does not support this combination of data types. The top-level FPGA VI cannot include a cluster control or indicator with both name controls and other data types. You must separate name controls and other data types into different clusters.
−61241 Duplicate file error. Two of the files specified though an IP Integration Node or component-level IP object have the same name but different contents. Rename one of the two files and adjust your design as necessary. For example, if your file is a VHDL file with an entity name that matches the filename, you may need to change the entity name and all the references to it. Alternatively, adjust the design to use only one of the files. File path 1: <userFilePath1> File path 2: <userFilePath2>
−61240 Duplicate file error. One of the files specified though an IP Integration Node or component-level IP instance has the same name as a file that LabVIEW creates. Rename the file and adjust your design as necessary. For example, if your file is a VHDL file with an entity name that matches the filename, you may need to change the entity name and all the references to it. File path: <userFilePath>
−61237 Terminal(s) requiring constant input wired to non-constant source(s). One or more terminals on this object must be wired to a constant. For example, if the FPGA I/O Node is in a non-reentrant VI, ensure that you wire a constant to the FPGA I/O In input of the FPGA I/O Node.
−61236 Terminal(s) requiring constant input unwired. One or more terminals on this object must be wired to a constant. Refer to the LabVIEW Help for information about the requirements of this object.
−61198 Handshake methods are not supported outside SCTLs. <MethodName> for <HandshakeName> is not supported outside single-cycle Timed Loops (SCTLs). Handshake methods are only supported inside SCTLs.
−61197 Each handshake cannot support more than one of each type of method. You have used multiple instances of the same <MethodName> method for the <Scope> handshake. Use only one Write method and only one Read or Read Without Acknowledge and Acknowledge method. If you use a Clear method, ensure there is only one.
−61196 The handshake Read Without Acknowledge and Acknowledge methods must be used in the same clock domain.
−61195 The handshake Read Without Acknowledge and Acknowledge methods cannot be used separately. The Read Without Acknowledge and Acknowledge methods must be used together for the <Scope> handshake. Add the missing method in the same clock domain.
−61194 You cannot use a handshake Read method with a Read Without Acknowledge or an Acknowledge method. For the <Scope> handshake, <MethodName> method was used with a Read method. Either use only a Read method or use a Read Without Acknowledge method and an Acknowledge method.
−61193 The handshake is missing a Read or Write method. The <Scope> handshake requires both a Write and a Read or a Read Without Acknowledge method. This <Scope> handshake is missing a <MethodName> method.
−61192 A False constant is wired to a DSP48 node enable terminal. The enable terminal should be wired to a dynamic signal or a True constant.
−61191 The IP Integration node specifies an incompatible .ngc synthesis file. <ngcFileName> was generated with a version of the Xilinx compilation tools that is not supported by this version of LabVIEW. Ensure you have the correct version of the Xilinx compilation tools by installing the tools from the Platform media that accompanies the version of LabVIEW you are using.
−61190 Inconsistent clock settings between CLIP declaration file and CLIP instantiation. The number of CLIP clocks in CLIP instantiation <clipInstanceName> is not the same as that in the CLIP declaration <clipDeclarationName>, or the HDL name, LabVIEW name, and/or port direction is not identical. Navigate to the Clock Selections category of the Component-Level IP Properties dialog box, check the changes, and click OK if you agree to accept them. Alternatively, change the CLIP declaration to make it consistent with the instantiation.
−61189 CLIP refers to an FPGA clock that does not meet requirements. CLIP instance <clipInstanceName> refers to FPGA clock <fpgaClockName> which does not meet the frequency requirements specified in the CLIP declaration <clipDeclarationName> for the clock <clipDeclarationClockName>. Select an FPGA clock that meets the frequency requirements of the CLIP instance or change the CLIP declaration to relax the clock <clipDeclarationClockName> frequency requirements.
−61188 CLIP refers to a missing FPGA clock. CLIP instance <clipInstanceName> refers to FPGA clock <fpgaClockName>, which is missing from the project. Select an FPGA clock already present in the project or add a clock with the name <fpgaClockName> to the project.
−61187 Missing CLIP implementation file. File <implementationFileName> specified in the CLIP declaration <declarationName> is missing. The file may have been deleted, renamed, or moved on the disk. Rescan the CLIP declaration files in the Component-Level IP category of the FPGA Target Properties dialog box for further information about this problem.
−61186 Updated CLIP declaration file. The CLIP declaration file was updated on disk since it was associated with this LabVIEW project. Rescan the CLIP declaration in the Component-Level IP page of the FPGA Target Properties dialog box. File: <filePath>
−61185 Missing CLIP declaration. The specified CLIP declaration file is missing. Update the CLIP declaration file path in the Component-Level IP page of the FPGA Target Properties dialog box or make sure that the file is present in the specified location. File Path: <filePath>
−61184 Incorrectly configured CLIP instance. CLIP instance <name> is configured with a CLIP declaration that is not valid. Change the CLIP instance configuration or add the relevant CLIP declaration to the target.
−61179 Unsupported node on this target. This target does not support the <NodeName> node. Change your algorithm to use blocks supported by the current target or obtain a target that supports the <NodeName> node.
−61178 Internal software error(s): Unable to resolve clock for ports. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: An object is requesting more than one clock, however it does not specify which ports on the object are synchronous to which clocks.
−61177 Missing Read or Write method for FIFO. Each FIFO requires either a Read or Write method, as applicable. Please add a Read or Write method for <FIFONAME>.
−61176 Invalid clock utilized for FIFO Method. The method connected to <PortName> of'<FifoName> utilizes <CurrentClk>, which is not permitted in this design. This method can exist only within the same clock domain as the Read or Write method of the associated FIFO. Note: For Get Stream State only, the default clock domain, <DefaultClk>, is also permitted. Given this design, the permitted clocks are: <ClockList>.
−61175 FPGA FIFO Node is not wired with constant FPGA FIFO Name.
−61174 FPGA Memory Node is not wired with constant FPGA Memory Name.
−61173 Item does not match configuration of the name control. The name control or constant wired to the method node does not match the configuration of the node.
−61172 Project item not found. The name control or constant is configured for an item that does not appear under the current target in the Project Explorer window. Add an appropriate item to the Project Explorer window or select a different item from the control or constant.
−61171 Name control or constant is empty. Empty value is not supported. Select an appropriate item that appears under the current target in the Project Explorer window.
−61164 Local and global variables of this type are not supported. Replace the variable with a control or constant.
−61163 Internal software error(s). <Message> An internal software error has occurred. Please contact National Instruments technical support at ni.com/support.
−61162 Object must be used inside a single-cycle Timed Loop. An object that must be used inside a single-cycle Timed Loop is being used outside a single-cycle Timed Loop.
−61161 VI Execution Mode not supported outside single-cycle Timed Loop. The Execution Mode of the selected VI is Inside Single-Cycle Timed Loop, but the VI is placed outside any timed loops. Move the VI into a single-cycle Timed Loop or change the Execution Mode in the configuration dialog box.
−61160 VI Execution Mode not supported inside single-cycle Timed Loop. The Execution Mode of the selected VI is Outside Single-Cycle Timed Loop, but the VI is placed inside a timed loop. Move the VI outside any single-cycle Timed Loops or change the Execution Mode in the configuration dialog box.
−61158 Conditional terminal on For Loop not supported. FPGA targets do not support using the conditional terminal on For Loops. Right-click the For Loop border and remove the checkmark next to Conditional Terminal.
−61157 Object(s) not supported in the single-cycle Timed Loop. Look-Up Table 1D with interpolation takes more than one clock cycle to execute. Turn off interpolation mode, remove the VI from the single-cycle Timed Loop, or replace the single-cycle Timed Loop with a While Loop.
−61155 Unsupported Clock For Resource. The <method> <IOType> for <IOResource> is used in a clock domain that it does not support. The supported clock domains include: <SupportedClockList>.
−61154 Access from different clock domains not supported. I/O resource <IOResource> does not support <methodList> accessed from a different clock domain.
−61153 Express VI not configured. The <express_vi> VI has not been configured. Double-click the <express_vi> VI on the block diagram to display the configuration dialog, verify the settings in the dialog, and click the OK button to save the settings.
−61152 Variable clock rate not supported. The Square Wave Generator VI is not supported with a variable clock. Change the top-level clock and reset the FPGA clock rate parameter on the Square Wave Generator VI.
−61151 Function or structure must be wired to a fixed clock name. Reconfigure the block diagram so that the clock name cannot be changed at run time.
−61150 Clock project item not found. The FPGA clock control or constant is configured for a clock that does not appear under the current target in the Project Explorer window. Add the clock to the Project Explorer window or select a different clock from the control or constant.
−61149 Clock control or constant is empty. The FPGA clock control or constant is empty. Select a clock that appears under the current target in the Project Explorer window.
−61148 Clock rate mismatch. The block diagram clock rate does not match the clock rate for which the Square Wave Generator VI was configured. The diagram clock is set to <diagram_clock> and the Square Wave Generator VI clock is set to <square_wave_clock>. Reconfigure the Square Wave Generator VI for the new clock rate. You might also need to modify computed values for the scaled inputs.
−61147 Internal software error(s). The VI <PathToSearchingVI> searched for port <SearchedPort> and did not find it in the port list.
−61145 HDL Interface Node File Not Found. LabVIEW cannot find the file <FilePath>. Reconfigure the HDL Interface Node to point to the current location of this file or remove the reference to this file. Double-click the HDL Interface Node and select the External Files tab to reconfigure the node.
−61144 HDL Interface Node outside single-cycle Timed Loop. Selected HDL Interface Node is only configured for placement inside a single-cycle Timed Loop, but the node is placed outside the loop. Move or reconfigure the node. To reconfigure the node, double-click the node, select the Execution Control category, and reconfigure the Single-Cycle Timed Loop option.
−61143 Front panel control/indicator violates size restrictions. The control/indicator <ObjectName> with total size of <BitSize> bits exceeds the allowed control/indicator size. The maximum size for a control/indicator is <MaxSize> bits.
−61142 VI is broken. This VI has a broken Run button. Click the Run button and resolve the items in the Errors list before trying to compile.
−61140 The VI cannot be compiled because its type is not supported. Only standard VIs can be compiled.
−61139 Top-level clock rate has changed. Top-level clock rate does not match rate for which the Sine Wave Generator VI was configured. Reconfigure the Sine Wave Generator or the top-level clock so that their rates match. You also might need to modify computed values for the frequency (cycles/tick) input.
−61137 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: Directory specified by the FPGASourceFilesDirectoryPath or FPGASimSourceFilesDirPath resource file tag does not exist. Directory path: <Path>
−61136 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: Required constraints (.ucf/.xdc) file not found. FPGA Source Files Directory Path: <Path>
−61135 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: Required top VHDL file not found. File path: <Path>
−61134 HDL Interface Node inside single-cycle Timed Loop. Selected HDL Interface Node is configured only for placement outside a single-cycle Timed Loop, but the node is inside a single-cycle Timed Loop. Move or reconfigure the node. To reconfigure the node, double-click the node, select the Execution Control category, and reconfigure the Single-Cycle Timed Loop option.
−61133 Front panel control/indicator(s) crossing clock domains not supported in subVIs. A subVI is called from clock domain <SubVIsClock> but a control or indicator on the connector pane is accessed from clock domain <FPTerminalClock>. Controls and indicators in subVIs do not support crossing clock domains. Move front panel control or indicator terminals outside the single-cycle Timed Loop. Use a wire to pass data into or out of the loop in the different clock domain.
−61132 Front panel control/indicator(s) crossing clock domains is not supported in subVIs. The read and write interfaces to a control/indicator in a subVI are in different clock domains. Controls/indicators in subVIs do not support crossing clock domains. Change the VI such that all accesses to the control/indicator are in the same clock domain.
−61131 Internal software error(s). A resource component does not exist. An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61130 Too many resource interface requestors. There are too many objects requesting access to a resource interface. Reduce the number of requestors to <MaxRequestors>.
−61129 Top-level port has more than one driver. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support. Top-level port <PortName> has more than one driver.
−61128 Internal software error(s). Internal error while creating a plugin arbiter. An internal software error in LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61127 Internal software error(s). Resource interface <ResPortName> must be defined before use by selected component. An internal software error in LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61126 Internal software error(s). Resource <ResName> must be defined before use by selected component.
−61125 The top-level port was requested before the selected component created it. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support. The top-level port <PortName> was requested before the selected component created it.
−61124 A resource was requested before the resource database was initialized. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support. A resource was requested before the resource database was initialized.
−61123 Internal software error(s). A resource interface was requested with a conflicting configuration. An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61122 Internal software error(s). Unrequesting resource <ResName> is unsupported. An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61121 Internal software error(s). A clock <ClockName> was not found when making connections for component. An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support at ni.com/support.
−61120 Error attempting to remove register from component. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support. Error attempting to remove register from component.
−61119 Arbitration option not supported in the single-cycle Timed Loop. Object(s) are requesting access to a resource through resource interface(s) configured with the Always Arbitrate option, which is not supported inside the single-cycle Timed Loop. Change the arbitration option or replace the single-cycle Timed Loop with a While Loop. Refer to the LabVIEW Help for more information about arbitration options.
−61118 Unsupported function inputs. The selected function does not support arrays and/or clusters as inputs when used in the single-cycle Timed Loop. Unbundle clusters and/or index arrays to reach scalar data types or replace the single-cycle Timed Loop with a While Loop.
−61117 Unsupported function inputs. The selected function has arrays and/or clusters wired to its inputs, which is not supported by the LabVIEW FPGA Module. Index arrays and unbundle clusters to reach scalar data types.
−61116 Unsupported Compound Arithmetic inputs. The selected Compound Arithmetic function has arrays and/or clusters wired to its inputs. The Compound Arithmetic function only supports scalar types in the LabVIEW FPGA Module. Remove any arrays or clusters wired to the Compound Arithmetic function. Index arrays or unbundle clusters to reach scalar data types.
−61115 Non-reentrant subVI(s) used in different clock domains. The selected non-reentrant FPGA subVI is located in more than one clock domain. All instances of a non-reentrant FPGA subVI must be in the same clock domain because LabVIEW generates code for a non-reentrant FPGA subVI only once. First, save a copy of the FPGA subVI with a different name for each clock domain. Next, replace calls to the old FPGA subVI with calls to the new FPGA subVIs based on the clock domain that calls the FPGA subVI.
−61114 Non-reentrant subVI(s) used inside and outside a single-cycle Timed Loop. A non-reentrant FPGA subVI is located both inside and outside a single-cycle Timed Loop. All instances of a non-reentrant FPGA subVI must be either inside or outside a single-cycle Timed Loop but not both, because LabVIEW generates code for a non-reentrant FPGA subVI only once. Save a copy of the FPGA subVI with a different name and replace all calls to the original FPGA subVI inside single-cycle Timed Loops with calls to the new FPGA subVI.
−61113 Constant references not allowed. The selected object is a constant reference. Constant unbound references imply runtime binding. The LabVIEW FPGA Module does not support statically unbound references. Remove the constant reference.
−61112 The method(s) are used in multiple clock domains. Object(s) are requesting access to a resource through method(s) in more than one clock domain. Ensure that all objects requesting access to the corresponding method are in the same clock domain.
−61111 Object(s) only supported in the single-cycle Timed Loop. The selected object is only supported inside the single-cycle Timed Loop. Place a single-cycle Timed Loop around the object.
−61110 Invalid FIFO implementation. An internal software error has occurred. The implementation of FIFO <Fifoname> is invalid. Use the FPGA FIFO Properties dialog box to select a valid implementation.
−61109 Object(s) connected to an initialized shift register. The selected object is connected to an initialized shift register. The selected object contains an embedded uninitialized shift register. Remove the initializer or use a Feedback Node.
−61108 Resource interface(s) requested from both inside and outside the single-cycle Timed Loop. Multiple objects are requesting access to a resource through a resource interface from both inside and outside the single-cycle Timed Loop, which is not supported. Place all objects requesting access to the resource interface either inside or outside the single-cycle Timed Loop.
−61107 Arbitration option not supported inside a single-cycle Timed Loop. Never Arbitrate is the only read port arbitration option supported inside a single-cycle Timed Loop.
−61106 Multiple instances of non-reentrant subVI(s) in the single-cycle Timed Loop. Non-reentrant subVI is called from multiple locations in the single-cycle Timed Loop(s), which is not supported. Change the diagram so that the subVI is called from only one place, use a While Loop instead of a Timed Loop, or change the subVI to be reentrant. Refer to the LabVIEW Help for more information about reentrant VIs.
−61105 Multiple writes to control/indicator and local(s) in single-cycle Timed Loops. Multiple writes to a control/indicator and corresponding local variable(s) are not supported in single-cycle Timed Loops. Create code in the single-cycle Timed Loop such that there is at most one write to a control/indicator or corresponding local variable. You can usually create such code by using a Case structure to select the data to write to a single instance control/indicator or local variable.
−61104 Arbitration option not supported in the single-cycle Timed Loop. Object(s) are requesting access to a resource through resource interface(s) configured with the Never Arbitrate option, which is not supported inside the single-cycle Timed Loop. Use the Arbitrate if Multiple Requestors Only option and make sure there is only a single object requesting access to the resource interface. Refer to the LabVIEW Help for more information about arbitration.
−61103 Arbitration option not supported in the single-cycle Timed Loop. Multiple objects are requesting access to a resource through a resource interface configured with the Arbitrate if Multiple Requestors Only option, which is only supported in the single-cycle Timed Loop if there is only a single requestor per interface. Remove the extra requestor(s), change the arbitration option if possible, or replace the single-cycle Timed Loop with a While Loop. Refer to the LabVIEW Help for more information about arbitration options.
−61102 Arbitration option not supported in the single-cycle Timed Loop. Object(s) are requesting access to a resource through resource interface(s) configured with the Always Arbitrate option, which is not supported inside the single-cycle Timed Loop. Change the arbitration option or replace the single-cycle Timed Loop with a While Loop. Refer to the LabVIEW Help for more information about arbitration options.
−61101 Object(s) not supported in the single-cycle Timed Loop. The selected object takes one or more clock cycles to execute. Remove the object from the single-cycle Timed Loop or replace the single-cycle Timed Loop with a While Loop.
−61100 The Interrupt function cannot wait until its interrupt is cleared in a single-cycle Timed Loop. The Interrupt function must have its Wait Until Cleared input unwired, or have a FALSE constant wired to this input.
−61097 CLIP simulation model not defined. CLIP declaration <clipDeclarationName> either has the top-level simulation behavior defined as "Exclude from simulation model" or does not have simulation behavior defined at all. A simulation model is necessary for simulation. Use the Configure Component-Level IP wizard to define a VHDL simulation model for the IP.
−61095 Object without implicit enable signal is used outside a single-cycle Timed Loop. An object has the implicit enable signal disconnected, but is used outside a single-cycle Timed Loop. If an object is outside a single-cycle Timed Loop, the object requires the implicit enable signal. Move the object inside a single-cycle Timed Loop or open the configuration dialog box for the object and remove the checkmark from the option to disconnect the implicit enable signal.
−61094 Object not supported in simulation. This object is not supported in simulation. Remove the object or disable it using a Conditional Disable structure.
−61093 Object without implicit enable in Case structure. Object has the implicit enable signal disconnected and is used in a Case structure. If an object is in a Case structure, the object requires the implicit enable signal. Move the object outside of all Case structures or open the configuration dialog box for the object and remove the checkmark from the option to disconnect the implicit enable signal.
−61092 Resource does not support single-cycle Timed Loops. The <method> <IOType> for <IOResource> is not allowed inside of a single-cycle Timed Loop.
−61091 Resource requires use inside single-cycle Timed Loop. The <method> <IOType> for <IOResource> must be used inside a single-cycle Timed Loop.
−61090 Resource used in unsupported clock domain. The <method> <IOType> for <IOResource> is used in a clock domain that does not support it. The supported clock domain is <RequiredClockDomain>. <AdditionalCLIPHelp>
−61065 Digital resource access conflict. The digital output resource <resource> cannot be accessed from both a Digital Line Output function and a Digital Port Output function. Use either the Digital Line Output function or Digital Port Output function, but not both.
−61064 HDL Interface Node configured to require clock during reset. HDL Interface Node is configured to require a running clock during reset. The clock domain this node is used in might stop during a reset. If registers inside your HDL are only asynchronously reset or you can guarantee your clock runs during a reset, reconfigure the node by double-clicking the node and removing the checkmark from the Requires Running Clock During Reset checkbox on the Execution Control tab. Otherwise, move the HDL Interface Node into a clock domain that is not external to the device and is not configured to support and require a run-time enable/disable.
−61063 Component requires a running clock during reset. A component is used in a clock domain that might stop. The component requires a running clock during reset to reset properly. Move the component from the clock domain that could stop to a clock domain that cannot stop.
−61062 Internal software error(s). LabVIEW expected to find a port named <portname> in the component clock information but did not find it. An internal software error has occurred. Please contact National Instruments technical support at ni.com/support.
−61058 Loops using external clocks must never exit. FPGA VIs do not support exiting loops that use external clocks. This restriction keeps improper block diagram execution contained within the loop if the clock glitches or setup/hold requirements are otherwise violated on flip-flops in the single-cycle Timed Loop. Unwire the conditional terminal for exiting the loop.
−61057 Internal software error(s). Clock resource <ClockResource> has the resource.xml tag for both ForceBufgInstantiation and ForceBufrInstantiation. FPGA code generation does not support both of these tags set on the same clock resource. Remove one of the tags.
−61056 Top-level clock cannot be enabled/disabled at run time. A clock for the top-level FPGA VI is configured to require run-time enable and disable. This configuration is not allowed because it prevents the FPGA VI from executing. Configure the top-level clock so that it does not support run-time enable and disable.
−61055 Clock requires enable and disable but is not programmed. A clock is configured to require run-time enable and disable, but the FPGA VI does not use the Start Enabling FPGA Clock or Start Disabling FPGA Clock function to program this clock. Use a Start Enabling FPGA Clock and Start Disabling FPGA Clock function with the clock or configure the clock to not support run-time enable and disable.
−61054 Cannot enable or disable a clock in the same clock domain being enabled or disabled. You cannot use the Start Enabling FPGA Clock VI or Start Disabling FPGA Clock VI in the same clock domain as the clock domain you want to enable or disable. Put these VIs in a different clock domain than the clock you want to enable or disable..
−61049 Enabling and disabling a clock requires the clock support run-time enable and disable. The clock wired to the Start Enabling FPGA Clock VI or Start Disabling FPGA Clock VI is not marked as supporting and requiring run-time enable and disable. Right-click on the clock you want to enable/disable and select Properties. In the Properties dialog, select the option Supports and Requires Runtime Enable and Disable. If this option is not available, the selected clock does not support run-time enable/disable.
−61047 Controls or indicators using Synchronous Display are not supported in single-cycle Timed Loops. Replace the single-cycle Timed Loop with a While Loop or deselect Synchronous Display on the control or indicator.
−61038 Millisecond timing resolution not supported. Timing function is configured to use milliseconds. However, an exact millisecond resolution is not possible within a clock domain with a frequency of <ClockRate> MHz. Change the timing function to use ticks or use a clock domain with a frequency that is a multiple of 1 kHz.
−61036 Microsecond timing resolution not supported. Timing function is configured to use microseconds, however an exact microsecond resolution is not possible within a clock domain with a frequency of <ClockRate> MHz. Change the timing function to use ticks or use a clock domain with a frequency that is a multiple of 1 MHz.
−61035 Microsecond/Millisecond timing resolution not supported. A timing function is configured to use microsecond or millisecond resolution, however the clock domain in which the function was placed uses a clock with a variable frequency. Change the timing function to use ticks or use a clock domain with a frequency that is not variable.
−61034 Invalid top-level clock for target. The currently configured top-level clock, <InvalidTopClockName>, for this FPGA target either does not exist in the project or is invalid. Select a valid top-level clock in the Properties of the FPGA target or add a valid clock with the name <InvalidTopClockName> to the project.
−61025 Enabling/Disabling derived clocks not supported. You have attempted to enable/disable a derived clock. You can enable/disable only base clocks that support and require run-time enable and disable.
−61011 Unsupported FIFO size. The selected FIFO is configured to use block memory implementation but contains less than two elements. Block memory FIFOs must contain at least two elements. Increase the size of the FIFO or use a different implementation for the FIFO.
−61009 Unresolved LabVIEW class. The LabVIEW class could not be statically resolved. Call chain: <CallChain>
−61008 Class control or indicator on top-level VI. The front panel of the top-level FPGA VI cannot contain LabVIEW classes when compiling.
−61007 Conditional Disable Structure contains broken code. The Conditional Disable Structure cannot be compiled while the conditional disable symbol FPGA_EXECUTION_MODE is set to THIRD_PARTY_SIMULATION.
−61006 Syntax error in user supplied HDL. The HDL compiler reported the following error(s):
−61005 Object not supported in simulation. Password protected VIs are not supported in simulation. You can either enter the password for the VI or remove the VI from the design.
−61004 FIFO object not supported in simulation. On this target, built-in control logic and target-optimal control logic for FIFOs are not supported in simulation exports. Use one of the following options to fix this error: remove the object, use the conditional disable structure to disable the object for simulation exports, or change the property of the FIFO control logic implementation to slice fabric.
−61003 You cannot include this function in a For Loop when the For Loop is inside a single-cycle Timed Loop.
−61002 The array size exceeds the limit for the current node when the node is inside a single-cycle Timed Loop. The array size exceeds the limit for the current node when the node is inside a single-cycle Timed Loop. To avoid this error, reduce the array size or move this operation outside of the Timed Loop.
61050 A parameter to a function is invalid.
61051 An operation did not complete because requested memory was unavailable.
61052 HDL code generation error occurred.
61053 A resource management error occurred. The resources might have conflicting configurations.
61054 A code generation error occurred while interpreting LabVIEW signals.
61055 Internal software error(s). An internal software error in the LabVIEW FPGA Module has occurred while generating code. Please contact National Instruments technical support at ni.com/support.
61056 Timing specified in the diagram cannot be met.
61057 Internally pipelined object(s) not connected to enough Feedback Nodes. The selected object has an embedded shift register that makes the output on a particular loop iteration correspond to the inputs from the previous iteration. Wire the outputs for the object directly to the minimum number of Feedback Nodes or uninitialized shift registers. You cannot wire the outputs to another object. Refer to the LabVIEW Help for more information about objects with embedded shift registers.
61059 Invalid initialization option on a Feedback Node that follows a Memory Read method. The FPGA VI contains a Feedback Node, following a Memory Read method, that ignores the FPGA Reset method. This configuration is not supported. Either change the initialization option on the Feedback Node or disconnect the initialization terminal.
61061 Unsupported delay on Feedback Node following memory read. The delay of the selected Feedback Node following a memory read is greater than 1 cycle. Configure the delay to be 1 cycle. You can place additional delays in a separate Feedback Node after this node.
61062 Invalid use of the enable terminal on a Feedback Node that follows a Memory Read method. The enable terminal is wired on a Feedback Node that follows a Memory Read method. To fix this error, right-click the Feedback Node and select Show Enable Terminal to remove the checkmark from this option. If you need the enable terminal, place the Memory Read method and Feedback Node inside a Case structure and wire the case selector terminal with the wire you intended to wire to the enable terminal of the Feedback Node. This workaround adds a mux on the output tunnel of the Case Structure, which reduces efficiency.
61063 Initializer constant is wired through a tunnel. A Feedback Node is configured to ignore the Reset method but has an initializer terminal that is wired to a constant that is wired through a tunnel. If the Feedback Node ignores the Reset method, you must wire the constant directly to the initializer terminal without going through a tunnel. An alternative is to configure the Feedback Node to initialize on the first call to the FPGA VI.
61064 Internal software error(s). An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with following information: Code Generation quit.

WAS THIS ARTICLE HELPFUL?

Not Helpful