Use Sampling probes in host VIs or FPGA VIs to check intermediate values on a wire as a VI runs and to view changes in signal data over time. For example, you can use Sampling probes to debug VIs in a single-cycle Timed Loop or in code that is intended for a single-cycle Timed Loop. With Sampling probes, you can visualize multiple signals on a waveform graph and compare how the value of each signal changes cycle by cycle.
|Note Sampling probes support only scalar, non-cluster data types, such as fixed-point numbers, Booleans, and integers.|
To view data from Sampling probes, use the Sampling Probe Watch Window. You cannot use the Sampling Probe Watch Window to change data. Sampling probes have no effect on the way a VI runs.
A sampling source determines when LabVIEW reads or samples data from associated probes. The sampling source ensures that Sampling probes update at the correct times relative to other Sampling probes associated with that source. There is no limit on the number of sampling sources you can specify. All probes associated with a given sampling source display on the same waveform graph in the Sampling Probe Watch Window.
The following table indicates some of the differences between sampling sources in the host VI and the FPGA VI:
|Target||Available Sampling Sources||Automatically Created?||Sampling Behavior|
|Host||For Loops and While Loops||No. You must first specify a sampling source before you use the Sampling probe in a host VI.||LabVIEW reports probe data when the sampling source loop finishes executing an iteration.|
|FPGA||FPGA simulated time
|Yes||LabVIEW reports probe data on each rising edge of the clock associated with the single-cycle Timed Loop containing the probe.|
|Note Because LabVIEW reports probe values when a loop designated as a sampling source completes execution, it is possible for a given probe to return multiple values in one iteration. For example, a probe might have multiple values in one iteration if the probe is in a For Loop or subVI that LabVIEW calls multiple times. The Sampling Probe Watch Window displays only the most recent data from the probe.|
Complete the following steps to designate a loop as a sampling source on the block diagram of a host VI:
LabVIEW automatically creates the FPGA sampling source using FPGA simulated time when you create the first Sampling probe. This sampling source is not tied to any individual structure on the block diagram, but you must use it within a single-cycle Timed Loop.
Complete the following steps to add a Sampling probe to the block diagram: