Controller Configuration Page

NI VeriStand 2018 Help

Edition Date: May 2018

Part Number: 372846M-01

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In the System Explorer window, select Controller from the configuration tree to display this page. Use this page to configure the timing of the VeriStand Engine, which is the system of timed loops that control the execution of your system, and communication between the target and the host computer.

This page includes the following components:

  • Target Specification—Includes the following components:
    • Name—Specifies the name of the system. The name you specify replaces Controller in the configuration tree.
    • Operating System—Specifies the operating system of the target. You can select from the following options:
      • PharLap
      • VxWorks
      • Windows—(Default)
      • Linux_32_ARM
      • Linux_x64
    • IP Address—Specifies the IP address of the target.
  • Processor Assignments—Includes the following components you can use to specify the processors on which to execute the Primary Control Loop and the Data Processing Loop of the VeriStand Engine:
    • Primary Control Loop mode—Specifies the mode to use to determine the processor on which the Primary Control Loop runs. You can select from the following options:
      • Automatic—(Default) The RT scheduler determines the optimal processor on which to execute the loop at each iteration.
      • Manual—Executes the loop on the processor you specify in the Processor field. If the target has multiple processors, National Instruments recommends you select this option so the RT scheduler does not compromise your system timing by repeatedly determining the optimal processor.
    • Processor—Specifies the processor on which to execute the loop. The default is -2 (any available processor). If you specify an invalid processor, the loop executes on the first available processor.
    • Data Processing Loop mode—Specifies the mode to use to determine the processor on which the Data Processing Loop runs. You can select from the following options:
      • Automatic—(Default) The RT scheduler determines the optimal processor on which to execute the loop at each iteration.
      • Manual—Executes the loop on the processor you specify in the Processor field. If the target has multiple processors, National Instruments recommends you select this option so the RT scheduler does not compromise your system timing by repeatedly determining the optimal processor.
    • Processor—Specifies the processor on which to execute the loop. The default is -2 (any available processor). If you specify an invalid processor, the loop executes on the first available processor.
  • Target Decimations—Includes the following component you can use to specify how frequently various loops get updated data from the Primary Control Loop:
    • Data Processing Loop—Specifies how frequently the Data Processing Loop reads values from the Primary Control Loop. The default is 1, which means the Data Processing Loop reads the values every time the Primary Control Loop executes. However, if you know the values in the system channels table do not change that frequently, you can specify a higher value to speed the execution time of the entire system. For example, if you specify 10, the Data Processing Loop reads values only on every tenth iteration of the Primary Control Loop.
  • Other Settings—Includes the following components:
    • Maximum streamed channels—Specifies the maximum number of channels that the VeriStand Engine can stream to the host. The default is 512.
    • Execution mode—Specifies the execution mode for the loops of the VeriStand Engine. You can select from the following options:
      • Parallel—(Default) Executes all the loops of the VeriStand Engine in parallel. In this mode, the system only writes values to and initiates execution of the Model Execution Loop(s) on the first iteration of the system, but it does not read values from the loop(s). On the second and subsequent iterations, the system reads values from the previous execution of the Model Execution Loop(s). This causes a one-cycle delay on executing your model(s), but can increase the execution speed of the entire system, especially on multi-core targets.
      • Low Latency—Executes all the loops of the VeriStand Engine in parallel, but writes values to, executes, and reads values from the Model Execution Loop(s) at every iteration of the system, including the first. National Instruments recommends you select this mode only if you need to minimize the latency between your inputs, model execution, and outputs. Waiting for the Model Execution Loop(s) to read, execute, and write on each iteration can significantly slow the execution speed of the system.
    • Filter DAQ Errors—Specifies whether to filter errors from NI-DAQmx function calls. Select this option if you do not want the system to shut down when an NI-DAQ device reports an error. The DAQ Error system channel still registers filtered errors, so you can monitor that channel to keep track of DAQ errors if you select this option.
    • Filter Watchdog Errors—Specifies whether to filter errors reported by the timing watchdog. For example, if you set the Primary Control Loop to execute at a high rate and your system contains large or complex models, the watchdog reports an error if the models cannot execute quickly enough to keep up with the Primary Control Loop. Select this option if you want NI VeriStand to ignore these errors.
    • FPGA / Scan interface mode—Specifies the interface mode for the NI Scan Engine on RT targets. You can use this option to override the current settings of the NI Scan Engine, which can be useful for certain C Series modules, such as NI 986x series devices. This option is disabled and has no effect on Windows targets.

      You can select from the following options:
      • Use current—(Default) Uses the currently configured NI Scan Engine interface mode. NI VeriStand does not override any settings.
      • FPGA Mode—Sets the NI Scan Engine to LabVIEW FPGA Interface mode.
      • Scan Mode—Sets the NI Scan Engine to Scan Interface mode.
      Note  Refer to your C Series device documentation for more information about Scan Interface and FPGA Interface modes.
    • DAQ DIO Rate—Specifies the rate in hertz at which the DIO Loop reads and writes DAQ digital line values. The default is 100 Hz.
    • Warmup Time—Specifies the amount of time in seconds that the system must wait before it can begin recording late counts. Use this option to avoid receiving late count errors due to expected jitter in the first few seconds after initializing system execution.
  • Timing Source Settings—Includes the following components you can use to specify the timing of the system:
    • Primary Control Loop timing source—Specifies the timing source for the system. The timing source times the system by sending ticks to the Primary Control Loop. You can select from the following options:
      • Automatic Timing—(Default) NI VeriStand determines the timing source to use. If you specify a valid timing device as the chassis master hardware synchronization device on the Chassis configuration page, NI VeriStand uses that device as the timing source. If you do not specify a valid timing device on that page, NI VeriStand selects the first available timing device. Timing devices can include NI-DAQ devices with at least one analog input channel, any NI FPGA device, or a custom device. If the system does not include a valid timing device, NI VeriStand uses the Target Rate you specify to time the system.
      • DAQ Timing—NI VeriStand uses an NI-DAQ device in the system as the timing source. Add an NI- DAQ device with at least one analog input channel to the configuration tree to enable this option.
      • Custom Device Timing—NI VeriStand uses the custom device you specify as the timing source.
    • Target Rate—Specifies the rate of the target in Hz. The default is 100. If your system definition does not include a valid hardware or custom device timing source, NI VeriStand uses this value to time the execution of the Primary Control Loop.
    • Timing Source Timeout—Specifies how long, in seconds, the Primary Control Loop waits to receive its first tick from the timing source before timing out.
    • Timing source setting—[Primary Control Loop timing source: DAQ Timing] Specifies the timing source setting for the Primary Control Loop:
      • Control Loop From Task—(Default) Creates a timing source that uses a combination of the sample clock and the sleep time to determine when to send ticks to the Primary Control Loop.
      • Signal From Task (Sample Complete)—Creates a timing source that sends a tick to the Primary Control Loop each time the Master DAQ device finishes acquiring samples from its AI channels.
    • Master DAQ device—[Primary Control Loop timing source: DAQ Timing] Specifies the DAQ device to use as the master timing device for the Primary Control Loop. You can only select devices that you have added to the system definition.
    • DAQ timeout—[Primary Control Loop timing source: DAQ Timing] Specifies how long to wait for the DAQ device to transfer data before timing out.
    • Timed loop sleep time—[Primary Control Loop timing source: DAQ Timing] Specifies in microseconds the amount of time the Primary Control Loop sleeps after each tick. The default is 0. NI VeriStand ignores this value if the device has an external timing source.
    • Master Custom Device—[Primary Control Loop timing source: Custom Device Timing] Specifies the custom device to use as the master timing source. Any timing and sync device or any custom device that includes a timing source VI can be a master timing device.
      Tip  You can use the Timing Source Initialization VI Template.vit, located in the Custom Device API library at labview\vi.lib\NI VeriStand\Custom Device API\Custom Device API.lvlib, as a template for a timing source VI in a custom device. You also can use the VIs on the Timed Structures palette in LabVIEW to create a custom timing source. Refer to the LabVIEW Help for more information about timed structures.

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