Creating a Custom FPGA Bitfile

NI VeriStand 2018 Help

Edition Date: May 2018

Part Number: 372846M-01

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Complete the following steps to create a custom FPGA bitfile.

  1. Make a copy of the sample FPGA VI and project.
  2. Customize the FPGA VI.
  3. Compile the FPGA VI into a bitfile.

Making a Copy of the Sample FPGA VI and Project

Complete the following steps to make a copy of a sample FPGA VI and project.

  1. Browse to the <Common Data>\FPGA\Templates directory.
  2. Create a copy of NI VeriStand IO PXI-7831R.lvproj in the same directory and open the copy in LabVIEW.
  3. Expand the PXI-7831R (PXI-7831R) item under My Computer in the Project Explorer window.

    This example project defines a PXI-7831R device as the target. If you are using this configuration, proceed to step 6. If you are using a different configuration, you must create a new FPGA target for the device. Complete the following steps to add a new device to the project.
    1. Right-click My Computer and select New»Targets and Devices from the shortcut menu.
    2. Select the New target or device option in the Targets and Devices dialog box.
    3. Select the device type from the list and click the OK button to close the dialog box and add the device.
    4. In the Project Explorer window, drag NI VeriStand FPGA DMA IO.vi from the PXI-7831R (PXI-7831R) target to the new target. Also drag the DMA_WRITE and DMA_READ FIFOs, and the FPGA I/O folders from the original target to the new target. The FPGA VI shows broken wires from any FPGA I/O Nodes with undefined channels.
    5. Refer to the LabVIEW FPGA Module documentation for information about adding I/O to the project.
  4. Double-click NI VeriStand FPGA DMA IO.vi in the Project Explorer window to open the VI.
  5. Select File»Save As from the pull-down menu of the NI VeriStand FPGA DMA IO VI window. Ensure the Substitute copy for original option is selected and click the Continue button.
  6. Rename the VI and save it to the <Common Data>\FPGA\Templates directory or any other directory you choose.
  7. Save the project by clicking the Save button in the Project Explorer window.

The next step is customizing the FPGA VI.

Customizing the FPGA VI

The process of creating a custom FPGA VI differs depending on the hardware devices you are using.

The default project defines the following FPGA I/O items for the PXI-7831R device: analog input channels 0–7, analog output channels 0–7, digital lines 0–39 on connectors 1 and 2, and digital lines 0–15 on connector 0. You can add or remove FPGA I/O items depending on the device and the needs of the project. For example, the PXI-7811R device has 160 DIO lines available; however, by default this sample FPGA VI uses only the first 40 lines on connectors 1 and 2. You can add more FPGA I/O items to this project if you want to use the additional DIO lines available on the PXI-7811R. Conversely, the PXI-7811R has no analog inputs or outputs, so if you are using this device, you can remove the analog I/O items from the project and the corresponding FPGA I/O Nodes from the FPGA VI.

Similarly, the default sample FPGA VI defines the digital lines on connector 0 as 8 PWM inputs and 8 PWM outputs. You might want more or fewer PWM channels. You might also add other custom I/O not defined in the sample FPGA VI.

Modify the FPGA VI, paying attention to the following guidelines:

  • Do not modify, remove, or rename any block diagram objects in the gray areas of the sample FPGA VI.
  • Do not modify the read and write code except to change the number of read and write packets or to change the size of the array constant for the DMA read operation of the DMA_WRITE FIFO.
  • As you create controls that represent parameters, ensure that the name of each control is unique within the VI.
  • Do not use the following control/indicator names: Loop Rate (usec), Write to RTSI, Use External Timing, Reset, Start, or Generate IRQ.

Refer to the LabVIEW FPGA Module documentation for more information about creating FPGA VIs and bitfiles for an FPGA target.

Transferring Data between the FPGA and the Host Computer

While you are creating or modifying the FPGA VI, knowing how NI VeriStand transfers data to and from the host computer is important. NI VeriStand uses direct memory access (DMA) FIFOs to transfer data between the host computer and FPGA target. The DMA_READ FIFO sends data read from the FPGA inputs to the host computer. The DMA_WRITE FIFO transfers data from the host computer to the FPGA outputs. The data is stored in packets that each can contain up to 64 bits. For example, you can pack four 16-bit signed (I16) integer values into a single 64-bit packet. You can pack values of different data types together in the same packet. If you add a channel to the FPGA VI, you also must add the channel to a packet that is written to the FIFO. Consider using the Join Numbers function or Split Number function to construct packets.

If the number of packets in either the DMA_READ or DMA_WRITE FIFO is greater than 15, you must update the FIFO size. Complete the following steps to update the size of the FIFO.

  1. In the Project Explorer window, right-click either the DMA_READ or DMA_WRITE FIFO and select Properties from the shortcut menu to display the General page of the FPGA FIFO Properties dialog box.
  2. Change the Number of Elements.
  3. Click the OK button to close the dialog box and apply the changes.

When you are finished creating the FPGA VI, select File»Save to save this VI.

The next step is compiling the custom FPGA VI into a bitfile.

Compiling the Custom FPGA VI into a Bitfile

Complete the following steps to compile the custom FPGA VI and create the bitfile.

  1. Display the Project Explorer window.
  2. Right-click the FPGA VI in the tree and select Compile from the shortcut menu to compile the FPGA VI. LabVIEW then creates a bitfile for this VI.
  3. The compiler places the bitfile in a subdirectory, FPGA Bitfiles, relative to the project file directory. By default, the bitfile name is name of project_name of FPGA VI.lvbitx.

The next step is creating an FPGA configuration file.

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